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L4M Device
Level 4 Mapper TXC-03456 DATA SHEET DESCRIPTION
The L4M device maps a 139.264 Mbit/s asynchronous line signal into an AU-4 VC-4/STS-3c SPE signal. The SDH/SONET signal is transmitted via the add bus with timing derived from the drop bus, add bus, or external clock source. The L4M can compensate for up to a frame offset when using external timing and an external C1 pulse. An option is provided to generate TOH bytes, such as the A1 and A2 framing bytes, a C1 byte, and the H1 and H2 pointer bytes only in drop bus and external timing modes. The VC-4/SPE can be fixed to a known J1 reference when add bus timing is selected, or it can be positioned with a pointer value of 0 or 522 when drop bus or external timing is selected. In the drop direction, an optional pointer tracking machine is provided. In this mode, the L4M can compensate for up to a frame in offset. External access is provided for the POH bytes, in addition to internal processing capability. Serial access is provided for the overhead communications bits in the format. An alarm indication port is provided for ring configuration applications.
* Maps an asynchronous 139.264 Mbit/s tributary into an AU-4/VC-4 STS-3c/SPE. * Nibble or byte 139.264 Mbit/s line interface - G.751 receive and transmit performance monitoring (frame alignment, distant alarm indication) * SDH/SONET bus access - Drop/add byte buses - Optional drop bus AU-4 pointer tracking with framing delay compensation * SDH/SONET timing mode - Drop bus timing - Add bus timing - External timing with framing delay compensation * Microprocessor access - Intel I/O with separate address/data buses - Motorola I/O with separate address/data buses - Motorola I/O with multiplexed bus - Interrupt capability with individual mask bits * POH byte processing * Enhanced desynchronizer access * Testing features - Line loopback - SDH/SONET loopback 223-1
test generator and analyzer * Boundary scan capability (IEEE 1149.1) * 144-pin plastic quad flat package
SDH/SONET SIDE
Add Bus
m o .c U t4 e e h S ta a .D w w w
APPLICATIONS
* Add/drop multiplexers * Digital cross-connect systems * Broadband switching systems * Transmission equipment Alarm "O"-Bits Indication Interface Control Port P I/O
LINE SIDE
L4M
Level 4 Mapper
Drop Bus
TXC-03456
VCXO Boundary POH Interface Control Scan
U.S. Patents No.: 4,967,405; 5,040,170; 5,265,096; 5,548,534 U.S. and/or foreign patents issued or pending Copyright 2000 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation
TranSwitch Corporation * 3 Enterprise Drive * Shelton, Connecticut 06484 Tel: 203-929-8810 * Fax: 203-926-9453 * www.transwitch.com
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Transmit Clock In Receive Nibble or Byte Data Receive Clock Out Receive Clock In
Document Number: TXC-03456-MB Ed. 1A, January 2000
Transmit Nibble or Byte Data
*
USA
DATA SHEET
TABLE OF CONTENTS
Section Page Block Diagram ...................................................................................................................................... 3 Block Diagram Description ................................................................................................................... 4 Pin Diagram .......................................................................................................................................... 7 Pin Descriptions .................................................................................................................................... 8 Absolute Maximum Ratings ................................................................................................................ 19 Thermal Characteristics ...................................................................................................................... 19 Power Requirements .......................................................................................................................... 19 Input, Output and I/O Parameters ....................................................................................................... 20 Timing Characteristics ........................................................................................................................ 22 Operation ....................................................................................................................................... 40-61 Internal Device Operation .............................................................................................................. 40 External Device Operation ............................................................................................................. 57 Memory Map ....................................................................................................................................... 62 Memory Map Descriptions .................................................................................................................. 66 Package Information ........................................................................................................................... 89 Ordering Information ........................................................................................................................... 90 Related Products ................................................................................................................................ 90 Standards Documentation Sources .................................................................................................... 91 List of Data Sheet Changes ............................................................................................................... 93 Documentation Update Registration Form* ................................................................................... 95
L4M TXC-03456
* Please note that TranSwitch provides documentation for all of its products. Customers who are using a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product.
LIST OF FIGURES
Figure 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Page L4M TXC-03456 Block Diagram ....................................................................................... 3 L4M TXC-03456 Pin Diagram .......................................................................................... 7 Transmit Line Interface Timing ....................................................................................... 22 Receive Line Interface Timing ........................................................................................ 23 Add Bus Interface Timing (Add Bus) .............................................................................. 24 Add Bus Interface Timing (External Clock) ..................................................................... 25 Add Bus Interface Timing (Drop Bus Clock and C1) ...................................................... 26 Drop Bus Interface Timing .............................................................................................. 27 Transmit Overhead Comm Channel Timing ................................................................... 28 Receive Overhead Comm Channel Timing .................................................................... 28 Transmit Path Overhead Interface Timing ...................................................................... 29 Receive Path Overhead Interface Timing ....................................................................... 30 Transmit Alarm Indication Port Timing ........................................................................... 31 Receive Alarm Indication Port Timing ............................................................................ 32 Microprocessor Timing Read Cycle - Intel ...................................................................... 33 Microprocessor Timing Write Cycle - Intel ...................................................................... 34 Microprocessor Timing Read Cycle - Motorola .............................................................. 35 Microprocessor Timing Write Cycle - Motorola ............................................................... 36 Microprocessor Timing Read Cycle Multiplex Bus - Motorola ........................................ 37 Microprocessor Timing Write Cycle Multiplex Bus - Motorola ........................................ 38 Boundary Scan Timing .................................................................................................... 39 Pointer Interpretation State Diagram .............................................................................. 41 Test Generator, Analyzer and Loopback......................................................................... 49 Boundary Scan Schematic .............................................................................................. 52 Phase-Locked Loop......................................................................................................... 57 L4M 140 Mbit/s Line Interface ........................................................................................ 58 Use of Two L4M Devices in Ring Configuration .............................................................. 60 L4M TXC-03456 144-Pin Plastic Quad Flat Package .................................................... 89
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET BLOCK DIAGRAM
SDH/SONET SIDE
EXLOS DROPT EXC1 EXTC ENABT ACLK AC1J1 AC1 ASPE ADD ADn APAR RPOHF RPOHD RPOHC TPOHF TPOHD TPOHC TOCHC TOCHD ROCHC ROCHD BUILD BLOCK STUFF/ SYNC BLOCK 8 INPUT BLOCK TXDn TXC NIB ADD BLOCK PERFORMANCE MONITORING TRANSMIT FRAME ALIGNMENT DETECTOR TRANSMIT AIS DETECTOR
L4M TXC-03456
LINE SIDE
8
MOTOROLA MOTOROLA INTEL (TWO BUSES) (MULTIPLEXED) POH I/O 8 8 D7 - D0 Unused A7 - A0 SEL RD WR RDY INT MOTO MADBUS RAMCI D7 - D0 Unused A7 - A0 SEL RD/WR Unused DTACK IRQ MAD7 - MAD0 AS Unused SEL RD/WR DS DTACK IRQ
OVERHEAD COMM CHANNEL I/O
RAM
P I/O
RAIPD TAIPD TAIPC TAIPF RESET Alarms PTEN DCLK DC1J1 DC1 DSPE DDn DPAR HIGHZ POHDIS AISIND
ALARM INDICATION PORT RECEIVE AIS DETECTOR RECEIVE FRAME ALIGNMENT DETECTOR
5
PERFORMANCE MONITORING POINTER TRACKING BLOCK 8 DECODE BLOCK DESTUFF BLOCK DESYNC BLOCK OUTPUT BLOCK RXDn RXCO RXCI
DROP BLOCK 8
Note: n = 7 - 0
BOUNDARY SCAN
TCK TMS TDI TRS TDO DESYNC SIGNALS
6
Figure 1. L4M TXC-03456 Block Diagram
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET BLOCK DIAGRAM DESCRIPTION
L4M TXC-03456
A simplified block diagram of the L4M device is shown in Figure 1. A byte-wide or nibble-wide 139.264 Mbit/s signal (TXDn) is connected to the Input Block. The nibble interface is selected by placing a high on the lead designated as NIB. Data is clocked into the L4M on positive transitions of the clock signal TXC. A control bit is provided which enables data to be clocked into the L4M on negative transitions of the clock. The L4M Input Block also terminates an external loss of signal (EXLOS) indication. A low placed on this lead indicates that an external line interface device, such as a CMI interface device, has detected a loss of signal. This signal is reported as an alarm within the L4M for the microprocessor, and can generate an interrupt and a 140 Mbit/s AIS when enabled. The 140 Mbit/s transmit line signal is monitored by the two Transmit Performance Monitoring Blocks for ITU-T G.751 frame alignment and a Distant Alarm Status. A Distant Alarm is defined as a 1 in bit 13 of the G.751 frame format. This alarm can generate an interrupt indication when enabled. When frame alignment is established, framing errors are counted in a 16-bit performance counter. The 140 Mbit/s line signal is also monitored for an Alarm Indication Signal (AIS). The AIS detection circuit can be enabled to work in conjunction with the frame alignment circuit. An AIS condition is reported as an alarm, and can generate an interrupt when enabled. The Stuff/Sync Block contains a FIFO and is controlled by write timing from the Input Block, and by read timing from the Build Block. The FIFO accommodates input and timing jitter as specified in ITU-T Recommendation G.823. The FIFO is protected against overflow and underflow conditions by reporting a FIFO error alarm, and will automatically recenter when a FIFO underflow or overflow alarm has been detected. The reset is held for approximately one frame before the FIFO is released for operation. Upon power-up, or on applying a reset, the transmit FIFO is also recentered. The stuffing algorithm uses one set of five control bits (C-bits) with one stuff opportunity bit (S-bit) per subframe (nine subframes) for frequency justification. The Build Block, with timing signals exchanged with the Stuff/Sync Block, constructs the VC-4 format as illustrated below.
1 1 J1 139.264 Mbit/s Build Format Subframe 1 Subframe 2 P O H 9 Subframe 9 R: C: S: O: I: Fixed Stuff Bits Justification Control Bits Justification Opportunity Bits Overhead Bits Information Bits 261
POH W 96I X 96I Y 96I Y 96I Y 96I W=I I I I I I I I X = CRRRRROO Y = RRRRRRRR Y 96I Y 96I Y 96I X 96I Y 96I Z =I I I I I I SR
X 96I Y 96I Y 96I Y 96I X 96I
Y 96I Y 96I X 96I Y 96I Z 96I
The L4M can build the 261 column by 9 row VC-4 format without or with path overhead bytes, and "O"-bits, depending on the features selected. The addition of POH bytes to the VC-4 format is disabled by applying a low to the pin designated POHDIS (also applying a low to POHDIS disables receive VC-4 POH processing). The starting position of the VC-4 J1 bytes can be synchronized to the add bus J1 pulse, when add bus timing is selected, or have a starting location of 0 or 522, when drop bus or the external timing modes are selected. The L4M can also generate an unequipped or supervisory unequipped VC-4. An unequipped VC-4 is defined as all zeros for the POH and payload bytes, while a supervisory unequipped VC-4 is defined as having valid POH bytes, but the payload bytes equal to zero. The Build Block is also responsible for multiplexing individual
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
L4M TXC-03456
POH bytes from the Path Overhead interface, or from RAM locations written to by the microprocessor, into the add bus data stream. The RDI state and FEBE count may be provided from a mate L4M for path-protected ring configurations. The Add Block uses drop bus timing signals, add bus timing signals, or external timing signals for outputting the SDH/STS-3c data signal and parity to the add bus. A feature is also provided that generates the A1, A2, C1 and H1/H2 Transport (SDH Section) Overhead bytes, depending upon the timing mode selected. The C1 byte value may be a fixed or a microprocessor-written value. The SS-bits in the transmitted pointer may be fixed or written by the microprocessor. Unused Transport Overhead bytes can be selected to be three-stated or forced to zero. In the add bus timing mode, the clock and C1J1 signals are monitored for operation. In the external timing mode, an option is provided which can compensate up to a frame for the position of the C1 byte framing pulse (EXC1). The Add Block interface for the add bus timing mode consists of an input clock (ACLK), input C1 and J1 indicator (AC1J1), a separate C1 input (AC1) when enabled, an input SPE indicator (ASPE), output byte data (AD7AD0), output parity indication (APAR), and an output add data to bus indicator (ADD). When the L4M is configured to operate in the external timing mode, the add bus signals consist of: external reference input clock (EXTC) and framing signal (EXC1) (optional), an output clock (ACLK), output C1 and J1 indicator (AC1J1), an output SPE indicator (ASPE), output byte data (AD7-AD0), output parity indication (APAR), and an output add data to bus indicator (ADD). When the L4M is configured to operate in the drop bus timing mode, the add bus signals consist of: an output clock (ACLK), output C1 and J1 indicator (AC1J1), an output SPE indicator (ASPE), output byte data (AD7-AD0), output parity indication (APAR), and an output add data to bus indicator (ADD). Odd parity may be calculated over all add bus signals (except the add indicator), or data only. The Drop Block terminates the drop bus signals. The drop bus signals consists of an input clock (DCLK), input C1 and J1 indicator (DC1J1), an input SPE indicator (DSPE), input byte data (DD7-DD0), input parity indication (DPAR), and an optional framing pulse (DC1). When the pointer tracking machine feature is enabled, the J1 signal in the C1J1 signal must not be present. Odd parity may be checked over all of the drop bus signals, or for the data byte only. When the pointer tracking machine is enabled, the relative position of C1 can be compensated up to one frame. The Pointer Tracking Block is enabled by placing a high on the lead designated as PTEN. The pointer tracking machine meets the pointer tracking requirements specified in ETSI 1015. The Pointer Tracking Block determines the starting location of the J1 byte in the VC-4 format. The S-bit transition check in the H1 pointer byte may be disabled in the Pointer Tracking Block. When enabled, the S-bit check can be a fixed value or a value written by the microprocessor. In addition, the AIS to LOP transition can be disabled to have the Pointer Tracking state machine conform to Bellcore standards. The Pointer Tracking Block monitors the pointer bytes for a path AIS and LOP alarm. Positive, negative and NDF occurrences are counted in 8-bit performance counters. Having established the starting location of the VC-4, the Decode Block performs Path Overhead byte processing. The POH bytes are written into RAM locations for a microprocessor read cycle in addition to being provided at a POH interface for external access. Capability is also provided in the L4M for performing the path trace message comparison for the J1 byte. B3 BIP-8 parity errors and the input FEBE count in the G1 byte are counted as bit or block errors. The status of the RDI bit is also checked, and an alarm indication provided. The FEBE count is also provided, along with an RDI indication (as a result of local alarms) to an Alarm Indication Port for path-protected ring operation. A bit stuffing AIS feature is also provided in addition to using an external AIS clock to generate line AIS as a result of receive alarms. The Desynchronizer Block is based on a proprietary TranSwitch design. The Desynchronizer Block removes the effect on the output signal of systemic jitter due to signal mapping and pointer movements, and consists of two FIFOs. The FIFOs are monitored for overflow and underflow alarms, and reset automatically when an alarm is detected. A 15-bit pointer leak register is provided for a microprocessor-written value. The following six desynchronizer signals are provided: Positive and negative phase detector outputs (CTRL and CTRL), a stuff indicator (STUFF) that provides the status of the stuff (justification) on a per-subframe basis, positive and negative justification indicator bits (PJ and NJ), and a pointer leak counter equal to zero indication (PLEQ0). In
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
L4M TXC-03456
addition, the desynchronizer pointer offset counter (9 bits plus sign value) is provided in the memory map for a microprocessor read, if required. The output of the Desynchronizer Block is connected to the L4M Output Block, Receive Frame Alignment Detector Block and Receive AIS Detector Block. The 140 Mbit/s receive line signal is monitored by the Receive Frame Alignment Detector Block for ITU-T G.751 frame alignment and the Distant Alarm Status. A Distant alarm is defined as a 1 in bit 13 of the G.751 frame format. This alarm can generate an interrupt indication when enabled. When frame alignment is established, framing errors are counted in a 16-bit performance counter. The 140 Mbit/s line signal is also monitored for an Alarm Indication Signal (AIS). The AIS detection circuit can be enabled to work in conjunction with the frame alignment circuit. An AIS condition is reported as an alarm, and can generate an interrupt when enabled. The Receive Frame Alignment Detector and Receive AIS Detector Blocks are disabled when the bit stuffing approach for generating 140 Mbit/s AIS is enabled and when the L4M generates a receive line AIS. AIS using a bit stuffing approach is implemented in the Decode Block prior to the Desynchronizer Block. A byte-wide or nibble-wide 139.264 Mbit/s signal (RXDn) is provided as an output from the Output Block. A nibble interface is selected by placing a high on the lead designated as NIB. Data is normally clocked out of the L4M on negative transitions of the clock signal RXCO. A control bit is provided which enables data to be clocked out of the L4M on positive transitions of the clock. External access to the Path Overhead bytes is provided by the POH I/O Block. The nine receive POH bytes present in the serial data channel (RPOHD) are clocked out on negative transitions of the gapped clock (RPOHC). A framing pulse (RPOHF), one clock cycle wide, identifies the starting location of the POH bytes, with bit 1 in the J1 byte. In the transmit direction, a gapped clock (TPOHC), and framing pulse (TPOHF) are provided. Serial data containing the POH bytes is clocked into the L4M on positive transitions of the clock. The B3 byte is present in the serial bit stream, but it is ignored by the L4M, and is recalculated. The framing pulse is one clock cycle wide and identifies the starting location of the POH bytes, with bit 1 in the J1 byte. An external AIS input is provided for generating a received 140 Mbit/s AIS and an RDI indication, if the POH bytes are processed externally. The Overhead Communications Channel I/O block provides an asynchronous interface for the 90 "O"-bits found in the SDH/SONET format. Serial data (ROCHD) which contains the "O"-bits, is clocked out of the L4M on negative transitions of the gapped clock (ROCHC). The received "O"-bits are not synchronized with the starting location of the frame. In the transmit direction, the "O"-bits (TOCHD) are clocked into the L4M by the gapped output clock (TOCHC). The Alarm Indication Port data output signal (RAIPD), consisting of the FEBE count and RDI indication, is clocked out of the L4M on negative transitions of the receive POH clock (RPOHC). The serial data consists of nine bytes each frame. The first four bits correspond to the FEBE count, which has been derived from the B3 BIP-8 parity check. The next bit, bit 5, corresponds to the RDI indication. Bits 6 and 7 are set to 0, while bit 8 is set to a 1. The received POH framing pulse (RPOHF) identifies the starting location of bit 1 in the first byte. In the transmit direction, the received serial data, framing pulse, and clock from the mate L4M become the data input (TAIPD), framing pulse input (TAIPF), and clock input (TAIPC). When the ring mode is selected, the mate L4M FEBE count and RDI indication are transmitted in the G1 byte. An upstream AIS indication may be inputted into the L4M using the E1 byte in the Transport (Section) Overhead bytes, or the external ISTAT, PAIS, and STAI pins. The upstream AIS indication can generate a 140 Mbit/s AIS, and a transmit RDI indication. The L4M supports three types of microprocessor interfaces: Intel microprocessor with separate address and data buses, Motorola microprocessor with separate address and data buses, and a Motorola microprocessor with a multiplexed address/data bus interface. The Boundary Scan block provides a mechanism for external access to the input and output pins of the device, so that they may be observed and tested. The structure and operation of this block are described in the Operation section.
TXC-03456-MB Ed. 1A, January 2000
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DATA SHEET PIN DIAGRAM
L4M TXC-03456
108
106
104
102
98
96
92
88
84
82
78
100
94
90
86
80
76
10
12
14
16
18
20
22
24
26
28
30
32
34
RESET PTEN TEST GND ROCHC ROCHD RAIPD RPOHD RPOHF VDD RPOHC TRS PJ CTRL CTRL GND EXAIS HIGHZ POHDIS NJ RXCI VDD RXCO AISIND RXD0 RXD1 RXD2 GND RXD3 RXD4 RXD5 RXD6 RXD7 VDD DROPT ENABT
Figure 2. L4M TXC-03456 Pin Diagram
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TXC-03456-MB Ed. 1A, January 2000
36
2
4
6
8
AD1 AD2 AD3 GND AD4 AD5 AD6 AD7 ADD VDD APAR AC1 ACLK ASPE AC1J1 GND EXTC DC1 DC1J1 DPAR DSPE VDD DCLK TEST DD0 DD1 DD2 GND DD3 DD4 DD5 DD6 DD7 VDD PLEQ0 TEST
74
AD0 TOCHC VDD EXC1 TEST TDI TMS TCK GND TAIPC TAIPF TOCHD TAIPD TPOHD VDD TPOHC TPOHF TEST TDO TEST GND TXC TEST EXLOS TXD7 TXD6 VDD TXD5 TXD4 TXD3 TXD2 TXD1 GND TXD0 NIB MOTO 72 70 112 68 114 66 116 64 118 62 120 60 122 124 126 128 130 132 48 134 46 136 44 138 42 140 40 142 38 144 110
L4M TXC-03456 PIN DIAGRAM (Top View)
58 56 54 52 50
STUFF AISCK VDD A7 A6 A5 A4 A3 GND A2 A1 A0 MADBUS AS VDD WR/DS RD,RD/WR SEL GND RAMCI GND RDY/DTACK INT/IRQ D7/MAD7 D6/MAD6 D5/MAD5 VDD D4/MAD4 D3/MAD3 D2/MAD2 D1/MAD1 D0/MAD0 GND STAI PAIS ISTAT
DATA SHEET PIN DESCRIPTIONS
POWER SUPPLY AND GROUND Symbol VDD GND Pin No. 10, 22, 34, 46, 58, 70, 82, 94, 106, 118, 130, 142 4, 16, 28, 40, 52, 54, 64, 76, 88, 100, 112, 124, 136 I/O/P* P P Type Name/Function
L4M TXC-03456
VDD: +5 volt supply voltage, 5% Ground: 0 volt reference.
*Note: I = Input; O = Output; P = Power
140 MBIT/S LINE INTERFACE Symbol TXC Pin No. 87 I/O/P I Type* TTL Name/Function Transmit 140 Mbit/s Line Clock: The clock rate is 34.816 MHz (nibble rate), or 17.408 MHz (byte rate). Byte or nibble-wide line data is clocked into the L4M on positive transitions of this clock when control bit TINVC is a 0. Data is clocked in on negative transitions of this clock when control bit TINVC is a 1. Transmit 140 Mbit/s Line Data: TXD7 (pin 84) is defined as the MSB for the byte interface, and is the first bit transmitted. For the nibble interface, TXD3 (pin 79) is defined as the MSB. TXD0 (pin 75) is the LSB for both the byte and nibble interfaces. External 140 Mbit/s Loss of Signal: An optional low input signal to report an external transmit 140 Mbit/s line loss of signal. If this lead is not used it must be connected to VDD. Receive 140 Mbit/s Line Data: RXD7 (pin 33) is defined as the MSB for the byte interface, and is the first bit received. For the nibble interface, RXD3 (pin 29) is defined as the MSB. RXD0 (pin 25) is the LSB for both the byte and nibble interfaces. Receive 140 Mbit/s Line Output Clock: The clock rate is 34.816 MHz (nibble rate), or 17.408 MHz (byte rate). Byte or nibble-wide line data is clocked out of the L4M on negative transitions of this clock when control bit RINVC is a 0. Data is clocked out on positive transitions of this clock when control bit RINVC is a 1. This clock is derived from the receive line input clock (RXCI). Receive 140 Mbit/s Line Input Clock: Byte (17.408 MHz) or nibble (34.816 MHz) clock used by the internal desynchronizer for sourcing data. This clock is used to derive the receive line output clock (RXCO). Nibble/Byte Data Selection: Common control lead for both the transmit and receive 140 Mbit/s interfaces. A high selects the interfaces as nibble, while a low selects the interfaces as byte.
TXDn (n=7-0)
84, 83, 81-77, 75 85
I
TTL
EXLOS
I
TTLp
RXDn (n=7-0)
33-29 27-25
O
TTL4mA
RXCO
23
O
TTL4mA
RXCI
21
I
TTL
NIB
74
I
TTL
*Note: See Input, Output and I/O Parameters section for Type definitions.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
SDH/SONET DROP BUS INTERFACE Symbol DCLK Pin No. 131 I/O/P I Type TTL Name/Function
L4M TXC-03456
Drop Bus Clock: Byte-wide data (DD7-DD0), parity (DPAR), payload indicator (DSPE), and the C1 and J1 pulses (DC1J1) are clocked into the L4M on negative transitions of this clock, which has a rate of 19.44 MHz. The clock signal is used for receive timing, and is monitored for loss of clock. Drop Bus Parity Bit: This input represents an odd parity calculation for each data byte, the DSPE signal, and the DC1J1 signal. When the internal pointer tracking feature is enabled, parity is calculated for data and the C1 pulse only. When a 1 is written to control bit PARDO, parity is calculated for the data byte only. Drop Bus C1J1 Indicator: The C1 pulse is an active high, one clock cycle wide timing pulse, that indicates the starting location of the first C1 byte time slot in the STM-1 or STS-3c frame when DSPE is low. When the pointer tracking feature is disabled, a J1 pulse, also one clock cycle wide, must be present to identify the starting location of the J1 byte in the AU-4 VC-4, or in the STS-3c SPE signal when DSPE is high. If the J1 pulse is not present, the pointer tracking feature must be enabled. The C1 pulse must be provided on this signal lead, or on the DC1 signal lead. Up to a frame in offset delay for the C1 byte can be compensated for when the pointer tracking mode is enabled. The receive offset delay is controlled by bit RC1DC in the memory map. Drop Bus SPE Indicator: A signal that is active high during the AU-4/STS-3c SPE time when the pointer tracking feature is disabled. This signal is not required when the pointer tracking feature is enabled. Drop Bus Byte: Byte-wide data that corresponds to the AU-4/ STS-3c signal from the drop bus. The first bit dropped corresponds to DD7 (pin 141). Drop Bus C1 Pulse: An external positive C1 pulse that may be provided on this pin instead of in the DC1J1 signal. This signal is or-gated internally with the DC1J1 signal to form a composite C1J1. When this signal lead is not used, it must be grounded.
DPAR
128
I
TTL
DC1J1
127
I
TTL
DSPE
129
I
TTL
DDn (n=7-0) DC1
141-137 135-133 126
I
TTL
I
TTL
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
SDH/SONET ADD BUS INTERFACE Symbol ACLK Pin No. 121 I/O/P I/O Type TTL4mA Name/Function
L4M TXC-03456
Add Bus Clock: The add clock is used for build timing, transmit FIFO, and for sourcing the add bus byte-wide data (AD7AD0) and parity (APAR), when add bus timing is selected. When external timing or drop timing mode is selected, this signal becomes an output. The add bus clock rate is 19.44 MHz. Add Bus C1J1 Indicator: The C1 pulse is an active high, one clock cycle wide, timing pulse that identifies the starting location of the first C1 byte time slot in the STM-1 or STS-3c frame. The C1 pulse may be provided on a separate lead (AC1) when the add bus timing mode is selected. A J1 pulse, also one clock cycle wide, identifies the starting location of the J1 byte in the AU-4 VC-4 or STS-3c SPE signal when the POH bytes are used. When the POH feature is disabled, the J1 pulse is not required. When external timing or drop timing is enabled this signal becomes an output. The C1J1 pulses correspond to the C1 and J1 bytes present on AD(7-0). When a 1 is written to control bit AC1EN, the C1 pulse may be provided on a separate lead (AC1) instead of in the AC1J1 signal. Add Bus Parity Bit: This output bit represents the odd parity calculation for each data byte (and SPE and C1J1, including AC1, when they are outputs). When a 1 is written to control bit PARDO, parity is calculated for the data byte only. APAR is not calculated over the unused TOH Byte times. Add Bus SPE Indicator: An input signal in add timing mode that is high during the AU-4/STS-3c SPE time. When the external timing or drop timing modes are enabled, this signal becomes an output. Add Data Byte: Byte-wide data that corresponds to the AU-4/ STS-3c signal to be placed on the add bus. The first bit transmitted corresponds to AD7 (pin 116). Data is three-stated during periods of no activity (e.g., during unused TOH times). Add Indicator: An active low signal that identifies the time slots corresponding to the output data (AD7-AD0). Add Bus C1 Pulse: This lead provides the C1 pulse as an output when the drop bus timing or external timing modes are enabled, and when the AC1EN control signal is a 1. The AC1J1 signal will contain the C1 pulse. When the add bus timing mode is enabled, this lead may be used as the C1 input, independent of the AC1EN control bit. This signal is or-gated internally with the AC1J1 signal in the add bus timing mode to form a composite C1J1signal. If this signal lead is not used in the add bus timing mode, it must be grounded.
AC1J1
123
I/O
TTL4mA
APAR
119
O
TTL4mA
ASPE
122
I/O
TTL4mA
ADn (n=7-0)
116-113 111-108
O
TTL4mA
ADD AC1
117 120
O I/O
TTL4mA TTL4mA
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
RECEIVE AND TRANSMIT PATH OVERHEAD BYTE INTERFACE Symbol RPOHF Pin No. 9 I/O/P O Type TTL4mA Name/Function
L4M TXC-03456
Receive Path Overhead Framing: A positive, one clock cycle wide, framing pulse that is synchronous with bit 1 in the J1 byte in the POH interface data. Receive Path Overhead Data: The serial output for the nine Path Overhead bytes: J1, B3, C2, G1, F2, H4, Z3, Z4, and Z5 bytes. The bytes are clocked out, starting with bit 1 in J1, on negative transitions of the clock signal (RPOHC) when the POH feature is enabled. Receive Path Overhead Clock: The nine POH bytes and RAIPD data are clocked out on negative transitions of this clock signal (RPOHC). Transmit Path Overhead Framing: A positive, one clock cycle wide, framing pulse that is synchronous with bit 1 in the J1 byte in the POH interface data. Transmit Path Overhead Data: A serial input for the Path Overhead bytes: J1, C2, G1, F2, H4, Z3, Z4, and Z5 bytes. The B3 byte time slot must be provided, but the contents are ignored by the L4M. The bytes are clocked in, starting with bit 1 in J1, on positive transitions of the clock signal (TPOHC). 8 bits are clocked in during the B3 Byte time, but they are ignored by the L4M device. The L4M recalculates the B3 byte parity value. The POH bytes are ignored when a low is placed on the POHDIS lead (pin 19). Transmit Path Overhead Clock: The transmit clock used for clocking in the Path Overhead bytes. Data is clocked in on positive transitions of the clock.
RPOHD
8
O
TTL4mA
RPOHC
11
O
TTL4mA
TPOHF
92
O
TTL4mA
TPOHD
95
I
TTL
TPOHC
93
O
TTL
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
RECEIVE AND TRANSMIT OVERHEAD COMM CHANNEL INTERFACE Symbol TOCHC Pin No. 107 I/O/P O Type TTL4mA Name/Function
L4M TXC-03456
Transmit Overhead Comm Channel Clock: An output clock provided for sourcing the transmit overhead communications channel data ("O"-bits). This clock has an effective data transfer rate of 720 kHz (8 kHz per bit, times 90 bits). Transmit Overhead Comm Channel Data: Data is clocked in on positive transitions of the clock signal (TOCHC). The data is unaligned in relationship to the overhead communications channel data bit placement in the SDH/SONET format. Receive Overhead Comm Channel Clock: A clock provided for outputting the transmit overhead communications channel data. This clock has an effective data transfer rate of 720 kHz (8 kHz per bit, times 90 bits). Receive Overhead Comm Channel Data: Data is clocked out on negative transitions of the clock signal (ROCHC). The data output for the overhead communications channel from the format is unaligned in relationship with the SDH/SONET frame.
TOCHD
97
I
TTL
ROCHC
5
O
TTL4mA
ROCHD
6
O
TTL4mA
EXTERNAL TIMING FOR ADD BUS Symbol EXTC Pin No. 125 I/O/P I Type TTL Name/Function External Clock Input: Enabled by placing a high on the ENABT lead (pin 36). Used for deriving output timing for the add bus. A clock rate of 19.44 MHz is required for AU-4/ STS-3c operation. This clock input is monitored for loss of clock. External C1 Input: Enabled by placing a high on the ENABT lead (pin 36). An optional C1 input signal that can be used for frame alignment. In addition, an option is provided for the pointer tracking feature which can compensate up to a frame in offset delay. If this pin is not used, it should be grounded.
EXC1
105
I
TTL
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
RECEIVE DESYNCHRONIZER Symbol CTRL Pin No. 14 I/O/P O Type Name/Function
L4M TXC-03456
CMOS4mA Phase Detector Output Positive: Normally connected to low pass filter as part of the desynchronizer phase-locked loop. See Figure 25. CMOS4mA Phase Detector Output Negative: Normally connected to low pass filter as part of the desynchronizer phase-locked loop. See Figure 25. TTL4mA Stuff (Justification) Opportunity Indication: This lead provides a status of the stuff (justification) S-bit in the Z byte for each row in the nine subframes in the 140 Mbit/s SDH/SONET format. The pin is high for one SONET/SDH row when there is a stuff indication, and low when this bit is information. The output on this pin is updated each row based on majority voting of the five c-bits. Positive Justification Indication: This lead provides a positive pulse when a positive pointer movement is detected. The pulse width is one DCLK cycle wide. Negative Justification Indication: This lead provides a positive pulse when a negative pointer movement is detected. The pulse width is one DCLK cycle wide. Pointer Leak Counter Equal to Zero Indication: This lead provides a positive indication when the internal pointer leak counter is equal to zero. This signal is reset to zero when the internal counter is preset. A positive pulse, one DCLK cycle wide, is then output for each time a bit is leaked out of the L4M's Desynchronizer. The last bit leaked out is represented by the last rising edge of the PLEQ0 signal lead.
CTRL
15
O
STUFF
72
O
PJ
13
O
TTL4mA
NJ
20
O
TTL4mA
PLEQ0
143
O
TTL4mA
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
RECEIVE AND TRANSMIT ALARM INDICATION PORT Symbol RAIPD Pin No. 7 I/O/P O Type TTL4mA Name/Function
L4M TXC-03456
Receive Alarm Indication Port Data: A serial output that provides the four-bit FEBE count (received B3 BIP-8 parity errors, bits 1-4), and Path RDI alarm indication (bit 5) for ring operation. Bits 6, 7, and 8 are set to 0, 0, 1, respectively. This lead is normally connected to the TAIPD lead at the mate 140 Mbit/s Mapper for ring operation. The RPOHC signal is used to clock out this signal. The RPOHF signal is used to provide the frame reference signal. The data output is disabled (forced to 0) when an active low is placed on the POHDIS lead. Transmit Alarm Indication Port Data: This serial input lead is normally connected to the RAIPD lead at the mate L4M for ring operation. Provides an input for the four-bit FEBE count (received B3 BIP-8 parity errors), and Path RDI alarm indication from the mate L4M. The data input is disabled when an active low is placed on the POHDIS lead. Transmit Alarm Indication Port Clock: This clock input is normally connected to the RPOHC clock lead at the mate L4M for ring operation. Transmit alarm data (TAIPD) is clocked into the L4M on positive transitions of the clock. This clock input is monitored for loss of clock. Transmit Alarm Indication Port Framing Pulse: Normally connected to RPOHF lead at the mate L4M for ring operation. Used to indicate the start of the external alarm indications for ring operation.
TAIPD
96
I
TTL
TAIPC
99
I
TTL
TAIPF
98
I
TTL
BOUNDARY SCAN Symbol TCK Pin No. 101 I/O/P I Type TTL Name/Function Test Boundary Scan Clock: The input clock for boundary scan testing. The TDI and TMS states are clocked in on positive transitions. Test Boundary Data Input: Serial data input for boundary scan test messages. Test Boundary Data Output: Serial data output whose information is clocked out on negative transitions of TCK. This pin requires a 4.7 k pull-up resistor if it is used. Test Boundary Mode Select: The signal present on this lead is used to control test operations. Test Boundary Scan Reset: An active low asynchronous reset signal. This lead should be held low if the boundary scan is not being used.
TDI TDO
103 90
I O 3-state I I
TTLp TTL4mA
TMS TRS
102 12
TTLp TTLp
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
OTHER PINS Symbol ENABT Pin No. 36 I/O/P I Type TTL Name/Function
L4M TXC-03456
Enable Add Bus Timing: Works in conjunction with the DROPT lead. The following table is the definition of the timing modes: ENABT 1 DROPT X Action External timing. Add bus timing derived from the external clock (EXTC) and the external framing pulse (EXC1). The ASPE, AC1J1, ACLK and AC1 signal leads become output leads. Add bus timing. Data derived from the add bus clock, ASPE, and AC1J1 input signals. Note: ASPE, AC1J1, AC1 and ACLK are inputs. Drop bus timing. Data, ASPE, AC1J1, and ACLK output signals are derived from the drop bus clock (DCLK) and C1 pulse in the drop bus DC1J1 signal.
0
0
0
1
DROPT ISTAT
35 37
I I
TTL TTL
Drop Timing Mode Enabled: Works in conjunction with the ENABT lead. See table above. External STS Alarm Indication: The purpose of this lead is to provide an upstream AIS indication for the L4M. This pin is enabled by writing a 1 to the EAPE control bit. A high on this lead generates AIS, and path RDI, when enabled. External Path AIS Indication: The purpose of this lead is to provide an upstream AIS indication for the L4M. This pin is enabled by writing a 1 to the EAPE control bit. A high generates line AIS, and path RDI, when enabled. STS Network Alarm Indication: This pin is enabled by writing a 1 to the XRDIEN control bit. A high generates a path RDI, when enabled. AIS Clock Input: Enabled when control bit BSAISE is a 0. This clock is used to generate transmit and receive 140 Mbit/s AIS on defined alarms. The clock frequency must be 34.816 MHz +/- 15 ppm for a nibble interface, and 17.408 MHz +/- 15 ppm for a byte interface. If AIS bit stuffing is used to generate AIS (control bit BSAISE is written with a 0), this clock is not required. External AIS Alarm Input: A low causes a receive 140 Mbit/s AIS when enabled, and a path RDI to be generated. May be used when processing received POH bytes via external circuitry (e.g., C2 byte).
PAIS
38
I
TTL
STAI
39
I
TTL
AISCK
71
I
CMOS
EXAIS
17
I
TTLp
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Symbol POHDIS Pin No. 19 I/O/P I Type TTLp Name/Function
L4M TXC-03456
Path Overhead Byte Processing Disabled: A low disables the insertion of the POH bytes (they are tri-stated) into the SPE from either the memory map RAM or the POH interface. It also disables the processing of the POH bytes in the receive direction and their subsequent actions. Receive AIS Indication Output: A low indicates that 140 Mbit/s AIS is being generated in the receive path. This pin is disabled when the BSAISE control bit=1 and the RLAISD alarm=1. However, when the L4M generates a receive line AIS, this pin will go low even if BSAISE=1 and RLAISD=1. High Impedance Enable: A low causes all output and bi-directional pins to three-state for test purposes. Pointer Tracking Enable: A high enables the internal pointer tracking feature. The pointer tracking feature determines the starting location of J1 in the dropped signal. The C1 pulse must be provided as the DC1, or DC1J1 signal. The J1 pulse must not be provided. The DSPE lead is ignored when the pointer tracking machine feature is enabled. A low requires the DC1J1 and DSPE signals to be provided as inputs. Hardware Reset: A low clears all performance counters, and presets the internal FIFOs and counters. All control bits (10H1FH) are preset to 0 except for bit 3 of register 13H and bit 0 of registers 1AH and 1BH. These 3 bits are preset to 1. This pulse must be present for a minimum of 200 nanoseconds. Note: The L4M requires approximately 1 microsecond upon power-up for stabilization before a low can be applied to this pin.
AISIND
24
O
TTL
HIGHZ PTEN
18 2
I I
TTLp TTL
RESET
1
I
TTLp
MICROPROCESSOR INTERFACE Symbol A(7-0) Pin No. 69-65 63-61 59 49-47 45-41 55 56 I/O/P I Type TTL Name/Function Address Bus (Motorola/Intel Buses): These are address line inputs that are used for accessing a RAM location for a read/ write cycle. A0 is the least significant bit. High is logic 1. Address Select (Multiplex Bus): A low is used for address select when the multiplex bus mode is selected. Data Bus: Bi-directional data lines used for transferring data. D0 is the least significant bit. Can also be used as multiplexed address and data bus with Motorola interface. High is logic 1. Select: A low will enable data transfers between the processor and the L4M RAM during a read/write cycle. Read (Intel mode) or Read/Write (Motorola mode): Intel Mode - An active low signal generated by the microprocessor for reading the L4M RAM locations. Motorola and multiplex Mode - An active high signal generated by the microprocessor for reading the L4M RAM locations. An active low signal is used to write to L4M RAM locations. - 16 TXC-03456-MB Ed. 1A, January 2000
AS D(7-0) MAD(7-0) SEL RD RD/WR
I I/O
TTL TTL8mA
I I
TTLp TTL
DATA SHEET
Symbol WR DS Pin No. 57 I/O/P I Type TTL Name/Function
L4M TXC-03456
Write (Intel mode): Intel Mode - An active low signal generated by the microprocessor for writing to the Mapper RAM locations. Motorola Mode - Not used. For the multiplex mode, this lead is used for the Data Select control. Ready (Intel mode) or Data Transfer Acknowledge (Motorola modes): This lead is three-stated. Intel Mode - A high is an acknowledgment from the addressed RAM location that the transfer can be completed. A low indicates that the L4M cannot complete the transfer cycle, and microprocessor wait states must be generated. Motorola and multiplex Mode - During a read bus cycle, a low signal indicates that the information on the data bus is valid. During a write bus cycle, a low signal acknowledges the acceptance of data. Interrupt: Intel Mode - A high on this output pin signals an interrupt request to the microprocessor. Motorola Mode - A low on this output pin signals an interrupt request to the microprocessor. Motorola/Intel Microprocessor Select: This lead works in conjunction with the MADBUS lead. A high selects a Motorola microprocessor compatible bus interface. A low selects the Intel microprocessor compatible bus interface. The following table summarizes the microprocessor selection. MOTO 0 1 1 MADBUS Action X Intel Microprocessor Interface, separate address/data buses. 0 Motorola Microprocessor Interface, separate address/data buses. 1 Motorola Microprocessor Interface, multiplexed address/data buses.
RDY/ DTACK
51
O
TTL8mA 3-state
INT/ IRQ
50
O
TTL4mA
MOTO
73
I
TTL
MADBUS
60
I
TTL
Multiplexed Address/Data Bus: When the MOTO lead is high, a high on this lead selects a Multiplexed Address/Data Bus interface, while a low selects separate Address/Data buses. This lead is disabled when MOTO is low. RAM Clock Input: Asynchronous clock input used for the internal L4M RAM operation. This clock must be connected to the microprocessor clock that has an operating rate of between 12 and 25 MHz with a duty cycle of 50 10%. This clock is also used as an internal time base for the loss of signal detectors.
RAMCI
53
I
CMOS
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
MANUFACTURE TEST PINS Symbol TEST TEST TEST TEST TEST TEST TEST Pin No. 144 89 91 104 86 132 3 I/O/P I I O I I I I Type TTLp TTLp TTL4mA TTLp TTLp TTLp TTLp Name/Function
L4M TXC-03456
Test Pin for Manufacture Testing: For normal operation this pin must be grounded. Test Pin for Manufacture Testing. For normal operation this pin must be grounded. Test Pin for Manufacture Testing: For normal operation this pin must be left unconnected. Test Pin for Manufacture Testing: For normal operation this pin must be grounded. Test Pin for Manufacture Testing: For normal operation this pin must be grounded. Test Pin for Manufacture Testing: For normal operation this pin must be grounded. Test Pin for Manufacture Testing: For normal operation this pin must be grounded.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage DC input voltage Ambient operating temperature Storage temperature range Symbol VDD VIN TA TS Min* -0.3 -0.5 -40 -55 Max* +7.0 VDD + 0.5 85 150
L4M TXC-03456
Unit V V
o
C
oC
*Note: Operating conditions exceeding those listed in Absolute Maximum Ratings may cause permanent failure. Exposure to absolute maximum ratings for extended periods may impair device reliability.
THERMAL CHARACTERISTICS
Parameter Thermal resistance junction to ambient Min Typ Max 23.0 Unit
oC/W
Test Conditions
POWER REQUIREMENTS
Parameter VDD IDD PDD Min 4.75 Typ 5.00 251 1.27 Max 5.25 320 1.68 Unit V mA W Inputs switching Test Conditions
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET INPUT, OUTPUT AND I/O PARAMETERS
Input Parameters For CMOS Parameter VIH VIL Input leakage current Input capacitance 3.5 Min 3.15 1.65 10 Typ Max Unit V V A pF
L4M TXC-03456
Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 5.25
Input Parameters For TTL Parameter VIH VIL Input leakage current Input capacitance 3.5 Min 2.0 0.8 10 Typ Max Unit V V A pF Test Conditions 4.75 Input Parameters For TTLp Parameter VIH VIL Input leakage current Input capacitance 0.5 3.5 Min 2.0 0.8 1.4 Typ Max Unit V V mA pF Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 5.25; Input = 0 volts
Note: Input has a 9k (nominal) internal pull-up resistor.
Output Parameters For CMOS4mA Parameter VOH VOL IOL IOH tRISE tFALL 2.5 2.0 5.5 3.9 Min VDD - 0.5 0.4 4.0 -4.0 9.9 8.0 Typ Max Unit V V mA mA ns ns CLOAD = 15pF CLOAD = 15pF Test Conditions VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 4.0
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Output Parameters For TTL4mA Parameter VOH VOL IOL IOH tRISE tFALL 2.5 1.0 5.5 2.0 Min VDD - 0.5 0.4 4.0 -2.0 10.0 4.0 Typ Max Unit V V mA mA ns ns CLOAD = 15pF CLOAD = 15pF
L4M TXC-03456
Test Conditions VDD = 4.75; IOH = -2.0 VDD = 4.75; IOL = 4.0
Input/Output Parameters For TTL8mA Parameter VIH VIL Input leakage current Input capacitance VOH VOL IOL IOH tRISE tFALL 1.9 0.8 4.5 1.5 VDD - 0.5 0.4 8.0 -4.0 8.0 3.1 3.5 Min 2.0 0.8 10 Typ Max Unit V V mA pF V V mA mA ns ns CLOAD = 25pF CLOAD = 25pF VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 8.0 Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 5.25
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET TIMING CHARACTERISTICS
L4M TXC-03456
Detailed timing diagrams for the L4M device are illustrated in Figures 3 through 21, with values of the timing parameters following each figure. All output times are measured with a maximum 75 pF load capacitance. Timing parameters are measured at (VOH + VOL)/2 or (VIH + VIL)/2 as applicable. Please note that all of the timing parameters in this document are subject to change contingent on the results of characterization. Figure 3. Transmit Line Interface Timing
tCYC tPWH TXC (INPUT) tSU tH TXD(8-0) (INPUT)
Note: Shown for TINVC equal to 0. Data is clocked in on negative transitions when control bit TINVC is equal to 1.
Parameter TXC clock period TXC duty cycle, tPWH/tCYC Data input set up time for TXC Data input hold time after TXC
Symbol tCYC
Min
Typ *
Max
Unit ns
40 tSU tH 5.0 10.0
60
% ns ns
* Nibble Interface: 28.7224 ns, Byte interface: 57.4449 ns.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 4. Receive Line Interface Timing
L4M TXC-03456
tCYC tPWH RXCI (INPUT) tD(1) RXCO (OUTPUT) tD(2) RXD(7-0) (OUTPUT) tPWL
Note: Shown for RINVC equal to 0. Data is clocked out on positive transitions when control bit RINVC is equal to 1.
Parameter RXCI clock period RXCI duty cycle tPWH/tCYC RXCO delay after RXCI Data output delay after RXCO
Symbol tCYC
Min
Typ *
Max
Unit ns
40 tD(1) tD(2) -2.0
60 23.0 9.5
% ns ns
* Nibble Interface: 28.7224 ns, Byte interface: 57.4449 ns.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 5. Add Bus Interface Timing (Add Bus) tCYC tPWH ACLK (INPUT) tH(2) ASPE (INPUT) AC1J1 (INPUT) AD7-AD0 (OUTPUT) ADD (OUTPUT) tSU(1)
C1(1)
L4M TXC-03456
tSU(2)
tH(1)
J1
tD(2)
DATA DATA DATA
J1 or Stuff
DATA
DATA
tD(1)
Note: The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. The APAR signal is not shown.
Parameter Add clock period Add clock duty cycle, tPWH/tCYC AC1J1 set-up time to ACLK AC1J1 hold time after ACLK ASPE set-up time to ACLK ASPE hold time after ACLK ADD low output delay from ACLK Data output delay from ACLK APAR output delay from ACLK
Symbol tCYC
Min
Typ 51.44
Max
Unit ns
40 tSU(1) tH(1) tSU(2) tH(2) tD(1) tD(2) tD(3) (not shown) 3.0 7.0 10.0 5.0 7.5 7.0 10.0
50
60
% ns ns ns ns
33.0 28.0 37.0
ns ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 6. Add Bus Interface Timing (External Clock) tCYC tPWH EXTC (INPUT) tH EXC1 (INPUT) ACLK (OUTPUT) ASPE (OUTPUT) AC1J1 (OUTPUT) AD7-AD0 (OUTPUT) ADD (OUTPUT) tD(3)
C1 J1
L4M TXC-03456
tPWL
tSU
C1
tD(1)
tD(2)
tD(4)
A1(2) A1(3) A2(1) A2(2) A2(3) C1(1) J1 DATA
tD(5)
Note: Shown for the TOHOUT control bit equal to 1 and the relationship to an optional external C1 pulse. The APAR signal is not shown.
Parameter External clock period Duty cycle, tPWH/tCYC Set up time for EXC1 for EXTC Hold time for EXC1 after EXTC Delay ACLK from EXTC Delay ASPE from ACLK Delay AC1J1 from ACLK Delay, data from ACLK Delay, ADD from ACLK Delay, APAR from ACLK
Symbol tCYC
Min
Typ 51.44
Max
Unit ns
40 tSU tH tD(1) tD(2) tD(3) tD(4) tD(5) tD(6) (not shown) 4.0 7.0 12.0 -6.0 -6.0 -6.0 -6.0 -6.0
50
60
% ns ns
28.0 6.0 6.0 6.0 6.0 11
ns ns ns ns ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 7. Add Bus Interface Timing (Drop Bus Clock and C1) tCYC DCLK (INPUT) DC1J1 (INPUT) ACLK (OUTPUT) tD(2) ASPE (OUTPUT) tD(3) AC1J1 (OUTPUT) AD7-AD0 (OUTPUT) ADD (OUTPUT)
C1 J1
L4M TXC-03456
tPWH
tPWL
tSU
C1
tH
J1
tD(1)
tD(4)
J1 DATA DATA DATA DATA DATA
tD(5)
Note: The C1 and J1 pulses must be present in the DC1J1 signal if the pointer tracking state machine is turned off. The add bus J1 pulse is shown for the SVC4H control bit set to 0. The APAR signal is not shown.
Parameter Drop clock period Duty cycle, tPWH/tCYC Set-up time for DC1J1 to DCLK Hold time for DC1J1 after DCLK Delay ACLK from DCLK Delay ASPE from ACLK Delay AC1J1 from ACLK Delay, data from ACLK Delay, ADD from ACLK Delay, APAR from ACLK
Symbol tCYC
Min
Typ 51.44
Max
Unit ns
40 tSU tH tD(1) tD(2) tD(3) tD(4) tD(5) tD(6) (not shown) 3.0 7.0 12.0 -6.0 -6.0 -6.0 -6.0 -6.0
50
60
% ns ns
28.0 6.0 6.0 6.0 6.0 11
ns ns ns ns ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 8. Drop Bus Interface Timing tCYC DCLK (INPUT) tSU(1) DD7-DD0 (INPUT) DSPE (INPUT) tSU(3) DC1J1 (INPUT)
C1(3) C1(1) C1(2) C1(3)
L4M TXC-03456
tPWH tH(1)
DATA DATA DATA J1 DATA DATA DATA
tSU(2)
tH(2)
tH(3)
J1
Note: The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the AU-4/STS-3c format there will be one J1 pulse, which indicates the start of the VC-4 that carries the 140 Mbit/s POH bytes and payload. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used it must be grounded. When the pointer tracking machine is selected, the J1 pulse and SPE signal are not required. The DPAR signal is not shown.
Parameter Drop clock period Duty cycle, tPWH/tCYC Data set up time for DCLK Data hold time after DCLK DSPE set up time for DCLK DSPE hold time after DCLK DPAR set up time for DCLK DPAR hold time after DCLK DC1J1 set up time for DCLK DC1J1 hold time after DCLK
Symbol tCYC
Min
Typ 51.44
Max
Unit ns
40 tSU(1) tH(1) tSU(2) tH(2) tSU(4) not shown tSU(4) not shown tSU(3) tH(3) 4.0 7.0 15.0 4.0 3.0 7.0 4.0 7.0
50
60
% ns ns ns ns ns ns ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 9. Transmit Overhead Comm Channel Timing tPWH TOCHC (OUTPUT) tSU tH TOCHD (INPUT)
L4M TXC-03456
tPWL
Note: The clock will be non-symmetrical.
Parameter TOCHC clock low time TOCHC clock high time TOCHD data set up time for TOCHC TOCHD data hold time after TOCHC
Symbol tPWL tPWH tSU tH
Min 668.7
Typ
Max 1183.1
Unit ns ns ns ns
668.7 10.0 7.0
Figure 10. Receive Overhead Comm Channel Timing
tPWH ROCHC (OUTPUT) tD ROCHD (OUTPUT)
tPWL
Note: The clock will be non-symmetrical.
Parameter ROCHC clock low time ROCHC clock high time ROCHD data output delay from ROCHC
Symbol tPWL tPWH tD
Min 668.7
Typ
Max 1183.1
Unit ns ns
668.7 -4.0 5.0
ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 11. Transmit Path Overhead Interface Timing tPWL TPOHC (OUTPUT) tPW TPOHF (OUTPUT) tD tPWH
L4M TXC-03456
tSU TPOHD (INPUT)
Bit 1 Byte J1
tH
Bit 2 Byte J1
Note: The clock will be non-symmetrical.
Parameter TPOHC clock high time TPOHC clock low time TPOHF framing pulse output delay for TPOHC TPOHD data in set up time for TPOHC TPOHD data in hold time after TPOHC TPOHF pulse width
Symbol tPWH tPWL tD tSU tH tPW
Min 668.7 668.7 -2.0 10.0 7.0
Typ
Max 1337.4 1337.4 5.0
Unit ns ns ns ns ns
1388.8
ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 12. Receive Path Overhead Interface Timing tPWL RPOHC (OUTPUT) tD(1) RPOHF (OUTPUT) tD(2) RPOHD (OUTPUT)
Bit 8 Byte Z5 Bit 1 Byte J1 Bit 2 Byte J1
L4M TXC-03456
tPWH
tPW
Note: The clock will be non-symmetrical.
Parameter RPOHC clock high time RPOHC clock low time RPOHF framing pulse output delay from RPOHC RPOHD data output delay from RPOHC RPOHF pulse width
Symbol tPWH tPWL tD(1) tD(2) tPW
Min 668.7 668.7 -2.0 -2.0
Typ
Max 1337.4 1337.4 5.0 5.0
Unit ns ns ns ns ns
1388.8
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 13. Transmit Alarm Indication Port Timing tPWL TAIPC (INPUT) tSU(2) TAIPF (INPUT) tSU(1) TAIPD (INPUT)
Bit 1 of Byte 1
L4M TXC-03456
tPWH
tH(2)
tH(1)
Bit 2 of Byte 1
Note: Alarm indication byte consists of eight bits repeated, nine times. Bit 8 in each byte is stretched. The first four bits correspond to the FEBE count (bits 1 through 4 in G1), bit 5 is the path RDI value, and bits 6 and 7 are set to 0, while bit 8 is set to 1.
Parameter TAIPC clock high time TAIPC clock low time TAIPD data set up time for TAIPC TAIPD data hold time after TAIPC TAIPF framing pulse set up time for TAIPC TAIPF framing pulse hold time after TAIPC
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2)
Min 617.3
Typ
Max 1388.8
Unit ns ns ns ns ns ns
771.6 3.0 7.0 3.0 7.0
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 14. Receive Alarm Indication Port Timing tPWL RPOHC (OUTPUT) tD(1) RPOHF (OUTPUT) tD(2) RAIPD (OUTPUT)
Bit 8 of Byte 9 Bit 1 of Byte 1 Bit 2 of Byte 1
L4M TXC-03456
tPWH
tPW
Note: Alarm indication byte consists of eight bits repeated, nine times. Bit 8 in each byte is stretched. The first four bits correspond to the FEBE count (bits 1 through 4 in G1), bit 5 is the path RDI value, and bits 6 and 7 are set to 0, while bit 8 is set to 1.
Parameter RPOHC clock high time RPOHC clock low time RPOHF framing pulse output delay from RPOHC RAIPD data output delay from RPOHC RPOHF pulse width
Symbol tPWH tPWL tD(1) tD(2) tPW
Min 617.3
Typ
Max 1388.8
Unit ns ns
771.6 -2.0 -2.0 1388.8 5.0 5.0
ns ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 15. Microprocessor Timing Read Cycle - Intel
L4M TXC-03456
tH(2) A(7-0)
D(7-0) tSU(1) SEL tSU(2) RD tD(2) RDY tPW(2) tH(1) tPW(1) tD(1) tF
Parameter Address set up time to SEL Data valid delay after RDY Data float time after RD SEL set up time for RD RD pulse width SEL hold time after RD RDY delay after RD RDY pulse width Address hold time after RD
Symbol tSU(1) tD(1) tF tSU(2) tPW(1) tH(1) tD(2) tPW(2) tH(2)
Min 10.0
Typ
Max
Unit ns
5.0 0.0 0.0 40.0 0.0 0.0 0.0 5.0 30.0 4.0 11.0
ns ns ns ns ns ns s ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 16. Microprocessor Timing Write Cycle - Intel
L4M TXC-03456
tH(1) A(7-0) tH(2) D(7-0) tSU(1) tSU(2) SEL tSU(3) WR tD tPW(2) RDY tWH tPW(1) tH(3)
Parameter Address hold time after WR Data hold time after WR Data valid set up time to WR Address valid set up time for SEL SEL set up time for WR WR pulse width RDY delay after WR RDY pulse width SEL hold time after WR RDY to WR
Symbol tH(1) tH(2) tSU(1) tSU(2) tSU(3) tPW(1) tD tPW(2) tH(3) tWH
Min 0.0 5.0 20.0 10.0 0.0 40.0 0.0 0.0 3.0 0.0
Typ
Max
Unit
ns ns ns ns ns 30.0 4 ns us ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 17. Microprocessor Timing Read Cycle - Motorola
L4M TXC-03456
tH(1) A(7-0)
D(7-0) tF(1) tSU(1) SEL tSU(2) RD/WR tD tF(2) tPW(1)
DTACK
tPW(2)
Parameter Address hold time after SEL Data float time after SEL Address valid set up time for SEL Read set up time for SEL Select pulse width DTACK pulse width Data output delay after DTACK DTACK float time after SEL
Symbol tH(1) tF(1) tSU(1) tSU(2) tPW(1) tPW(2) tD tF(2)
Min 5.0 0.0 10.0 5.0 40.0 0.0
Typ
Max
Unit
13.0
ns ns ns ns
4 0.0
us ns ns
0.0
10.0
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 18. Microprocessor Timing Write Cycle - Motorola
L4M TXC-03456
tH(1) A(7-0) tH(2) D(7-0) tSU(1) tSU(2) SEL tPW(1)
tSU(3) RD/WR
tH(3)
tF tPW(2) DTACK
Parameter Address hold time after SEL Data hold time after SEL RD/WR hold time after SEL Data valid set up time for SEL Address valid set up time for SEL Write set up time for SEL Select pulse width DTACK pulse width DTACK float time after SEL
Symbol tH(1) tH(2) tH(3) tSU(1) tSU(2) tSU(3) tPW(1) tPW(2) tF
Min 5.0 3.0 0.0 20.0 10.0 5.0 40.0 0.0 0.0
Typ
Max
Unit ns ns ns ns ns ns ns
4 10.0
us ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 19. Microprocessor Timing Read Cycle Multiplex Bus - Motorola tSU(1) SEL tSU(2) RD/WR tPW(1) AS tSU(3) DS tSU(4) tD(2) DTACK tD(1) MAD(7-0) tH(1)
Data
L4M TXC-03456
tH(4)
tH(3)
tH(2)
tD(3)
Address
Parameter SEL to AS, setup time RD/WR (read) to DS, setup time AS time AS to DS, setup time MAD(7-0) three-state to DS setup time Data out delay from DS DTACK active out delay from DS DTACK inactive out delay from DS Data out hold time after DS AS hold time after DS RD/WR (read) hold time after DS SEL hold time after DS
Symbol tSU(1) tSU(2) tPW(1) tSU(3) tSU(4) tD(1) tD(2) tD(3) tH(1) tH(2) tH(3) tH(4)
Min 20.0 20.0 20.0 20.0 20.0
Typ
Max
Unit ns ns ns ns ns
250.0 330.0 20.0 20.0 0.0 0.0 0.0
ns ns ns ns ns ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 20. Microprocessor Timing Write Cycle Multiplex Bus - Motorola
L4M TXC-03456
tSU(1) SEL tSU(2) RD/WR tPW(1) AS tSU(3) DS tD(2) DTACK tSU(5) MAD(7-0)
Address Data
tH(4)
tH(3)
tH(2)
tD(3)
tSU(6) tH(5) tH(6)
Parameter SEL to AS, setup time RD/WR (write) to DS, setup time AS time AS to DS, setup time DTACK active out delay from DS DTACK inactive out delay from DS Data in valid setup time for DS Data in hold time after DS AS hold time after DS RD/WR (read) hold time after DS SEL hold time after DS Address valid setup time for AS Address hold time after AS
Symbol tSU(1) tSU(2) tPW(1) tSU(3) tD(2) tD(3) tSU(6) tH(6) tH(2) tH(3) tH(4) tSU(5) tH(5)
Min 20.0 20.0 20.0 20.0
Typ
Max
Unit ns ns ns ns
330.0 20.0 20.0 0.0 0.0 0.0 0.0 20.0 0.0
ns ns ns ns ns ns ns ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 21. Boundary Scan Timing
tPWL tPWH
TCK (Input)
L4M TXC-03456
tH(1) tSU(1)
TMS (Input)
tH(2) tSU(2)
TDI (Input)
tD
TDO* (Output)
*Note: TDO is a three-state output. If this pin is used, it should be connected via a 4.7 k resistor to the +5 volt supply.
Parameter TCK clock high time TCK clock low time TMS setup time to TCK TMS hold time after TCK TDI setup time to TCK TDI hold time after TCK TDO delay from TCK
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tD
Min 50 50 3.0 2.0 3.0 2.0 -
Max
Unit ns ns
7.0
ns ns ns ns ns
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET OPERATION
L4M TXC-03456
The operations section is divided into two major sections: Internal Device Operation, and External Device Interfaces.
INTERNAL DEVICE OPERATION Timing Modes The L4M supports the following timing modes: drop bus, add bus, and external timing modes. In the drop bus timing mode, the drop bus clock (DCLK) and the C1 pulse (DC1J1 or DC1) before or after framing reference compensation, provide the time base for deriving the add bus signals which consist of clock (ACLK), data (AD(7-0)), C1 and J1 indicator (AC1J1 and AC1), SPE indicator (ASPE), add indicator (ADD), and parity (APAR). The add side J1 pulse is derived internally. The add bus starting location for the SPE may have a pointer value equal to 0 or 522. In the add bus timing mode, add bus timing signals are independent of the drop bus signals. Add bus timing is derived from add bus input signals which consists of a clock (ACLK), C1 and J1 indicator (AC1J1 and AC1), and SPE indicator (ASPE). The output signals consists of data (AD(7-0)), add indicator (ADD), and parity (APAR). The starting location of the SPE (J1 byte) is determined by the input J1 pulse (AC1J1), and SPE indicator (ASPE). In the external timing mode, the external timing signals are independent of the drop bus timing. The external timing signals consist of an external clock (EXTC) and optional frame reference pulse (EXC1). The L4M can also compensate for up to one frame of offset delay for the external C1 pulse. Add bus output timing is derived from the two external signals and consists of a clock (ACLK), C1 and J1 indicator (AC1J1 and AC1), SPE indicator (ASPE), data (AD(7-0)), add indicator (ADD), and parity (APAR). The add bus starting location for the SPE may have a pointer value equal to 0 or 522. The three timing modes are selected using two control pins, designated as DROPT (pin 35) and ENABT (pin 36). The following table lists the control lead states for selecting the timing mode. DROPT pin Low X High ENABT pin Low High Low Add Bus Timing External Timing Drop Bus Timing Timing Mode
Receive C1 Reference Delay When the pointer tracking feature is enabled by placing a high on the PTEN lead (pin 2), and control bit RC1DC (bit 3 in 18H) is written with a 1, a 12-bit register location (19H and 18H) is enabled which can compensate for up to 2429 positions (270 columns x 9 rows) for a dropped C1 reference pulse. For example, if a binary 0 is written into the 12-bit register by the microprocessor, the C1 pulse (in DC1J1 or DC1) must be in the C11 time slot (the correct time slot). When the binary value of 1 is written into the 12-bit register, it is assumed that the C1 pulse is shifted one time slot (one clock cycle) into the time slot that corresponds to the C12 byte. This means that the starting point for the frame reference should be one byte earlier. Values written into the 12-bit register greater than 2429 will be counted as a delay equal to 0.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
L4M TXC-03456
INC
3*any_point accept new offset
3*new_point accept new offset
DEC
inc_ind incr. offset
dec_ind decr. offset
3*new_point accept new offset
NORM
NDF
from all states 8*inv_point offset undefined 3*new_point accept new offset 3*AIS_ind offset undefined
NDF_enable accept new offset
LOP
AIS
8*NDF_enable offset undefined
Note: The AIS to LOP transition is not specified for North American applications, and can be disabled by setting the PADS control bit to a 1.
Figure 22. Pointer Interpretation State Diagram
Pointer Tracking Feature The pointer tracking feature is enabled by placing a high on the PTEN lead (pin 2). The AU-4 pointer is carried in the H1 and H2 bytes. The starting location for the frame is determined by the C1 pulse present in the DC1J1 or DC1 signal lead. When the pointer tracking feature is enabled, the J1 pulse in the DC1J1 signal must not be present, nor is the DSPE signal required. The pointer tracking machine derives the starting location of the J1 byte and the other VC-4 bytes. The pointer tracking state machine is compliant with the ETSI state machine specified in the ETSI 1015 document. A logic diagram of the state machine is shown in Figure 22. No additional states or transitions have been added to the pointer state machine. For North American applications, a control bit is provided for disabling the AIS to LOP transition, which is shown as a dotted line in Figure 22. This transition is disabled by writing a 1 to control bit PADS (bit 1 in 18H). In addition, control bits are provided which permit the value of the S-bits (H1 byte) in the pointer tracking machine to be disabled, equal to 10, or to a microprocessor-written value.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
The following table lists the control states associated with the SS-bits. RPSDS 0 0 1 RPSSEL 0 1 X Action
L4M TXC-03456
Pointer tracking machine uses 10 as the SS-bit value in the state machine. Pointer tracking machine uses microprocessor-written value for SS-bit check in state machine. SS-bit check in pointer tracking machine disabled. Pointer tracking machine ignores the SS-bits in the transition state definitions.
Path AIS and loss of pointer alarms are provided. In addition, pointer increments, decrements, and NDFs are counted in 8-bit performance counters. Upstream Receive AIS Indication An upstream AIS indication can be provided for the L4M in one of two ways: using the E1 byte in the Transport Overhead bytes, or control lead indications. The upstream AIS indication can generate a 140 Mbit/s line AIS and transmit path RDI, when enabled. Writing a 0 to control bit EAPE enables using the E1 byte for the upstream AIS indication. For example, the TranSwitch SOT-3 generates an AIS signal (all ones) in the E1 byte when a loss of frame, loss of signal, loss of pointer, or line or path AIS are detected. The L4M uses majority logic (five out eight ones) to determine if the E1 byte has an AIS indication (E1AIS alarm). The first and subsequent indications indicate the alarm condition. Recovery occurs on the first indication that the E1 byte does not have an all ones (AIS) state. This indication is to be used by the L4M to generate a receive AIS indication and path RDI, when enabled. When a 1 is written to the EAPE control bit it disables the detection of all ones in the E1 byte, and enables the ISTAT and PAIS leads. An active high on the ISTAT or PAIS lead causes the XISTAT and XPAIS alarms, and a 140 Mbit/s line AIS and path RDI when enabled. Receive Path Overhead Byte Processing The Path Overhead bytes consist of the J1, B3, C2, G1, F2, H4, Z3, Z4, and the Z5 bytes. All POH bytes are provided at the external POH interface, including the B3 byte. The POH bytes are also written into the L4M memory map for a microprocessor read cycle. Path Overhead Byte Processing is inhibited (and functions reset) when an active low is placed on the POHDIS lead (pin 19). POH processing (for C2 and J1) is also inhibited when any of the following alarms are detected: Drop Bus of the J1 pulse (DBLOJ1) when the PTEN pin is low Drop Bus loss of clock (DBLOC) E1AIS detected (E1AIS) when EAPE control bit is 0 PAIS Alarm pin equal to 1 (XPAIS alarm) when EAPE control bit is 1 ISTAT Alarm pin equal to 1 (XISTAT alarm) when EAPE control bit is 1 Receive loss of pointer (RLOP) when PTEN pin is high Receive path AIS (RPAIS) when PTEN pin is high
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Receive J1 Byte Processing
L4M TXC-03456
There are two possible received J1 message sizes, 16 bytes (ITU-T), or 64 bytes (ANSI). The L4M is capable of dimensioning the transmit (and receive) RAM memory segment to the two sizes (16-Byte or 64-Byte). In addition, two modes of operation are provided for the 16-byte (ITU-T) format: a microprocessor read mode, and a compare read mode. The following table lists the various control states associated with J1 processing. CCITT 0 J1COM X Action Transmit and receive J1 segments are configured for the 64-byte J1 message size. No relationship is required between the memory segment and the message written for transmission or for the message received. Transmit and receive J1 segments are configured for the 16-byte J1 message size. No relationship is required between the memory segment and the message written for transmission or the message received. Transmit and receive J1 segments are configured for the 16-byte J1 message size. No relationship is required between the memory segment and the message written for transmission. For the receive J1 bytes, a 16-byte microprocessor message is written into a 16-byte segment for comparison against the received message. The written message must start with the multiframe indicator written into the starting location of the segment. The L4M does not perform the CRC check in the 16-byte message.
1
0
1
1
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
L4M TXC-03456
The ITU-T defined 16-byte message consists of an alignment signal of (10000000 00000000) in the most significant bit (bit 1) of the message. The remaining 7 bits in each frame consists of a data message, as illustrated below. Bit 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 4 5 6 7 8
16-Byte J1 Message
ITU-T 16-Byte J1 Message Format The J1 16-byte message comparison works according to the following steps: 1. Assume that the L4M J1 detector is out of lock, and there is no mismatch alarm. 2. A 16-byte reference message is written into the memory map by the microprocessor. 3. The incoming message is received, and the J1 comparison circuit searches for the multiframe pattern (1000...0 pattern). 4. Multiframe is found. 5. The incoming (received) 16-byte message is then checked for three consecutive 16-byte message repeats. 6. If an error occurs before step 5 is completed, the sequence repeats, starting at step 3. 7. If the incoming 16-byte message repeats three times in row (after the multiframe is detected) without an error, the internal memory map segment is updated. This is an in-lock condition, and the J1 Loss of Lock alarm is reset. 8. This stable message is compared against the microprocessor-written message, byte for byte for 16-bytes (the length of the multiframe message). If they compare, a match is declared. No mismatch alarm. If they do not compare a mismatch alarm is declared. A J1 mismatch alarm results in RDI and AIS being sent continuously, when enabled. There is no out-of-lock alarm because the received message is stable. 9. If the microprocessor-writes a new byte, a J1 Trace Identifier Mismatch (J1TIM) alarm will also occur because the receive message is stable but there is mismatch between the two locations. A mismatch alarm is declared, and RDI and AIS are sent continuously, when enabled. There is no out-of-lock alarm because the received message is stable. 10. If the receive message changes for three consecutive 16-byte messages, an out of lock alarm occurs. However, the mismatch alarm resets. 11. The sequence repeats. When the J1 is not in lock (J1 lock equal to 0), a J1 loss of lock alignment alarm (J1LOL) is declared. This process is inhibited and reset during an incoming AIS condition.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Receive C2 Byte
L4M TXC-03456
The L4M provides C2 signal label mismatch detection between the received C2 byte, and a microprocessorwritten value and also a fixed 01H value in hardware, when enabled. When control bit C2FVD is written with a 1, the detection of the 01 value is disabled, and detection depends solely on the register value written by the microprocessor. Five or more consecutive mismatched signal labels in the C2 byte from the microprocessorwritten value or a label not equal to the 01H (when C2FVD=0) results in a path signal label error (PSLERR) alarm. The alarm state is exited when five or more consecutive matches, or the 01H value (when C2FVD=0) are received correctly. The L4M also provides an unequipped indication (C2EQ0) when the incoming C2 byte matches an internal 00H value for five consecutive frames. The alarm is exited when the C2 byte does not equal a 00H value for five or more consecutive frames. Please note that if the accepted path signal label value is all zeros (C2 unequipped), or an 01 (if C2FVD=0), a mismatch alarm (PSLERR) is not declared. The C2 mismatch detection and unequipped indication are disabled when any of the following alarms are detected. Loss of Drop Bus J1 Pulse (DBLOJ1) when the PTEN pin is low E1 AIS (E1AIS) (from the Drop bus) when EAPE is 0 ISTAT is a 1 when EAPE is 1 PAIS is a 1 when EAPE is 1 Receive loss of pointer (RLOP) when the PTEN pin is high Receive path AIS (RPAIS) when the PTEN pin is high
Receive G1 Byte The received states of the G1 byte are provided for a microprocessor read cycle, and are also provided at the path overhead byte interface, for external processing as required. Bits 1 through 4 in the G1 byte convey a FEBE count. There are nine possible valid FEBE values, 0 through 8. Other values are detected as a zero count. The FEBE value received is the count of interleaved bit blocks that have been detected in error in the received Path BIP-8 code at the far end. A 16-bit counter is provided for counting the number of FEBE bits or blocks received in error. Up to eight errors per frame may be counted. Bit 5 is the defined as the Path Far End Receive Defect Indication alarm (Path RDI) indication. A receive path RDI alarm indication (RRDI) occurs when the L4M detects a one for five or ten consecutive frames. Recovery occurs when the L4M detects a zero for five or ten consecutive frames. Writing a 1 to control bit RDI10 selects the detect and recovery value of 10 consecutive events. Bits 6, 7, and 8 in the G1 byte are unassigned and are normally received as 0s. They are provided for both a microprocessor read cycle and at the external POH interface. Receive Desynchronizer The rate at which the pointer leak buffer is to be leaked is written to the 15-bit pointer leak rate register. If enhanced desynchronizer operation is required, the following additional signals are provided: a stuff indication lead, positive and negative justification indications, and a pointer leak counter equal to zero indication lead. For controls, a LOADEN control bit and a 9-bit (plus sign bit) pointer offset counter are provided, in addition to the 15-bit pointer leak rate register.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Receive 140 Mbit/s Line AIS Generation
L4M TXC-03456
The L4M provides two techniques for generation of line AIS. The first approach uses an external clock, and the second approach uses a bit stuffing technique. The use of an external stable clock for AIS permits the receive performance monitoring circuit to be used (i.e., Receive AIS Detector and Receive Frame Alignment Detector), while the bit stuffing AIS approach disables the receive performance monitoring circuit when the L4M is generating a receive line AIS. Line AIS is defined as all ones in the data signal. In addition, in the receive direction, when BSAISE=1 line AIS cannot be generated when the drop bus clock is lost, since this clock is required for generating line AIS. When the bit stuffing AIS approach is not used and the L4M generates an RXAIS signal, the external PLL will lose lock. In this case the AISIND pin can be used with some external logic to cause the external 139.264 MHz VCXO to lock onto the AIS clock to maintain proper synchronization of the 139.264 MHz VCXO clock. Using an external clock for AIS generation is enabled by writing a 0 to control bit BSAISE (bit 0 in 1CH). Please note that control bit BSAISE is 0 upon power-up. The AIS clock is either 17.408 MHz for byte operation, or 34.816 MHz for nibble operation. The AIS clock is monitored for operation and an alarm indication (LAISC) provided when this clock is not functioning. Loss of AIS clock also prevents the L4M from generating a line AIS in either the transmit or receive directions. When the L4M is required to generate either a transmit or receive line AIS the external AISCK clock input is used as the timebase. The bit stuffing approach does not require an external clock. The capability to generate line AIS on alarm indications is enabled by writing a 1 to control bit BSAISE. In the transmit direction, line AIS is generated by bit stuffing 7/9 of the time using an all ones pattern for data. The actual technique consists of performing stuffing for the first four rows of the 9 subframes (CCCCC=1, and the S-bit is 0). Frequency justification is performed for row 5, bit stuffing for rows 6, 7, and 8, followed by frequency justification for row 9. In the receive direction, the approach is the same, bit stuffing is multiplexed into the format prior to the desynchronizer. In the transmit direction, line AIS cannot be transmitted when the drop clock is lost in the drop bus timing modes, in the add bus timing mode when the add bus clock is lost, or when the external clock is lost in the external timing mode. Receive and Transmit Performance Monitoring The L4M provides 139.264 Mbit/s receive and transmit performance monitoring. Performance monitoring includes frame alignment, providing the status of the remote indication alarm bit, counting framing errors and, when enabled, works in conjunction with the AIS detector circuits. The L4M monitors the receive and transmit data for frame alignment as specified in ITU-T Recommendation G.751. The frame structure consists of 2928 bits, starting with bit 1. The frame alignment pattern is carried in bits 1 through 12, and has the following frame alignment pattern: 111110100000. After frame alignment, a 16-bit performance counter counts the number of errored frames (one or more bits in the frame alignment pattern is in error) in both the transmit and receive directions. In addition, the status of the distant alarm indication (bit 13 in the format) is provided. A 1 causes a TDAI alarm (bit 5 in 28/29H), or a RDAI alarm (bit 4 in 28/29H), and an interrupt if the mask bit is enabled, and the hardware interrupt is enabled. No other action is taken upon detection of Distant Alarm Indication. An enable bit (LFAISE) is provided to generate a 140 Mbit/s AIS, when loss of frame alignment is detected. The frame alignment detection can be coupled with the AIS recovery circuit by setting the FDAEN control bit to 1. In the receive direction, the performance monitoring circuit (i.e., Receive AIS Detector and Receive Frame Alignment Detector) is disabled when the bit stuffing AIS feature is enabled and the L4M is generating a receive line AIS; also, the receive frame error counter is inhibited on a RLOF alarm or DBLOC alarm and the transmit frame error counter is inhibited on a TLOF alarm.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Transmit Unequipped Channel Generation
L4M TXC-03456
The L4M provides the capability of generating an unequipped channel or a supervisory unequipped channel. The following table lists the control bit states for generating the two types of unequipped channels and the priority associated with path AIS. TUNEQ 0 1 1 X POHEUQ X 0 1 X PAISG 0 0 0 1 Normal Operation Transmit Unequipped channel. POH bytes and payload bytes are equal to zero. Transmit supervisory unequipped channel. POH are transmitted (if enabled). Payload bytes are transmitted as zero. Transmit path AIS. POH (when enabled) and payload bytes transmitted as 1. Action
Transmit POH Bytes The insertion of the transmit POH bytes is enabled by placing a high on the signal lead labeled POHDIS (pin 19). This signal lead has priority over the control bits such as the POH enable control bit for unequipped status (POHEUQ). When an active low is placed on this pin, the insertion of POH bytes into the SPE is disabled. However, the POH RAM locations may still be written to by the microprocessor. The starting location of the payload (without the POH bytes) will be still determined by the J1 pulse (add bus timing), or at the 0 or 522 location (drop bus or external timing modes), determined by the SVC4H control bit. When enabled (POHDIS is high), the L4M has the capability of inserting the Path Overhead bytes from RAM locations, or from an external POH interface (except the B3 byte). The individual RAM locations are allowed to be updated during operation. The L4M is also equipped with a control bit (POHRAM) that permits the Path Overhead bytes (except the B3 byte) from the transmit POH interface (when selected) to be written into common RAM locations (or microprocessor-written values) in addition to being transmitted. The following are the control states associated with the POHRAM and EXbn control bits. POHRAM 1 EXbn 1 Action The external interface POH byte that is selected is transmitted and is also written into RAM. For example, when EXF2 is a 1, the external interface F2 byte is transmitted and written into the RAM each frame. The external POH byte that is selected is transmitted. The microprocessor can write a value to RAM as required. For example, when EXF2 is a 1, the external interface F2 byte is transmitted each frame, but is not written to the RAM location. Microprocessor-written POH byte is transmitted, except B3 and G1 bytes. See RING, FEBEEN and RDIEN control bits for more information.
0
1
X
0
This feature allows the microprocessor to read selected transmitted POH interface bytes prior to transmission for test purposes. In addition, this feature permits the user to switch back and forth between a selected POH I/O byte and the RAM location, without having to reinitialize the RAM POH byte locations during switch-over.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Transport (Section) Overhead Bytes
L4M TXC-03456
The L4M provides an option in the drop bus and external timing modes to provide selected Transport (Section) Overhead Bytes. This feature is selected by writing a 1 to control bit TOHOUT (bit 5 in 14H). The selected TOH bytes are the six A1 and A2 framing bytes, C1 byte, and the H1 and H2 pointer bytes (including Y and 1s pointer bytes). The A11, A12, and A13 bytes are equal to F6H, while A21, A22, and A23 are equal to 28H. When control bit UPC1 is a 0, the value 01H is transmitted as the C1 byte. When UPC1 is a 1, the microprocessor-written value in 17H is transmitted as the C1 byte. The pointer values H1 and H2 correspond to H11 and H21 in the AU-4 pointer (H11, H12, H13, H21, H22, H23), as illustrated below. The H11 and H21 bytes carry the pointer value that corresponds to 522 or 0, depending on the state of the SVC4H control bit. The H12 and H13 bytes carry the value 1001ss11. The H22, and H23 bytes are specified as all ones. H11 NNNNSSID H12 1001ss11 H13 1001ss11 H21 IDIDIDID H22 11111111 H23 11111111
Note: NNNN is equal to 0110. When control bit TPSSEL is a 0, the SS-bits are transmitted as a 10, while the SS-bits in H12 and H13 are undefined and are transmitted as 00. When a 1 is written into the transmit pointer S-bit select control bit TPSSEL, the microprocessor is able to program the SS and ss bits. Register 1DH has the following structure: Bit 7 TS 6 TS 5 Ts 4 Ts 3 Ts 2 Ts 1 RS 0 RS
Transmit H11
Transmit H12
Transmit H13
Receive H11
Transmit C1 Reference Delay (External Timing Mode Only) When the external timing mode is selected, and control bit TC1DC (bit 3 in 16H) is written with a 1, a 12-bit register location (19H and 18H) is enabled which can compensate for up to 2429 positions (270 columns x 9 rows) for the external C1 reference pulse. For example, if a binary 0 is written into the 12-bit register by the microprocessor, the external C1 pulse (in EXC1) is in the C11 time slot (the correct time slot). When the binary value of 1 is written into the 12-bit register, it is assumed that the C1 pulse is shifted one time slot (one clock cycle) into the time slot that corresponds to C12 byte. This means that the starting point for the transmit frame reference should be one byte earlier. Values written into the 12-bit register other than 2429 will be counted with a delay equal to 0. Add Bus C1 Input/Output Pulse When control bit AC1EN is a 1, in the drop timing mode and external timing modes, the C1 indicator pulse is provided as a separate output lead (AC1) instead of being in the C1J1 signal. In this mode, the C1J1 signal will carry the J1 pulse only. In the add bus timing mode, the AC1 lead is or-gated with the AC1J1 signal to form a composite internal C1J1 signal. The AC1 option is selected using the states defined in the table below: AC1EN 0 1 AC1 pin Low C1 pulse Action Normal operation. Pin is grounded. C1 is provided in the AC1J1 signal. In the drop timing and external timing modes, C1 is provided as a separate output signal. The AC1J1 signal contains the J1 signal only. In the add bus timing mode, the C1 signal may be provided in the AC1J1 signal or as a separate signal.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Test Generator and Analyzer
L4M TXC-03456
The L4M is equipped with a transmit test generator and receive analyzer. A simplified block diagram of the test generator and analyzer is shown in Figure 23 below. The transmit clock (TXC) must be present in order for the 223-1 test generator to function. The test generator sequence is specified in ITU-T recommendation O.151. The test generator is enabled by writing a 1 to control bit TGEN (bit 2 in 14H). The byte or nibble transmit input is disabled and the test sequence is enabled. The test generator can be also be enabled when the L4M is in line loopback. The 223-1 test analyzer samples the receive data for operation. The test analyzer is enabled by writing a 1 to control bit ANAEN (bit 1 in 14H). The test analyzer monitors the incoming test sequence for lock, using consecutive 1000-bit blocks (not a sliding window). An out of lock alarm (ANOOL) is detected when 30 bits in a 1000-bit sequence are detected in error. Recovery occurs when the first 24 bits in the test sequence match. Errors are counted in a 16-bit performance counter (locations 44 and 45H). The counter is inhibited when out of lock or when the analyzer is disabled.
Data
Desync Circuit
Clock
Output Block
Rec Data (Byte/Nibble) Rec Clock
Data Test Analyzer Enable
Receive Test Analyzer
NIB Lead
Loopback Enable
Test Generator Enable Data Clock
Xmit Data (Byte/Nibble) Xmit Clock Data Clock
Data Xmit FIFO Clock
Input Block
Test Pattern Clock
Transmit Test Generator
NIB Lead
Figure 23. Test Generator, Analyzer and Loopback
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Performance Counters
L4M TXC-03456
All 16-bit performance counters have a special 16-bit read operation which allows uninterrupted access, without the danger of one byte changing while the other byte is read. To perform a 16-bit read operation, the low order byte is read first. The read operation freezes the count in the high order byte. The high order byte should be read next. All the performance counters can also be configured to be either saturating or non-saturating. When a 0 is written to control bit COR (bit 0 in 13H), the performance counters are configured to be saturating, with the counters stopping at their maximum count. An 8-bit or 16-bit counter is reset on a microprocessor read cycle. Counts that occur during the read cycle are held, and the counter updated afterwards. When a 1 is written to control bit COR, the performance counters are configured to be non-saturating, and roll over after the maximum count in the counter is reached. In this mode, the counters do not clear on a microprocessor read cycle, but continue to count. All the performance counters can be reset simultaneously by writing a 1 to control bit RSETC (bit 7 in 1CH). This bit is self clearing, and does not require the microprocessor to write a 0 into this location afterwards. In addition, a performance counter can also be cleared by writing the value of 00H to the low byte, immediately followed by writing a 00H to address n+1. The n+1 address location contains the high order byte of the 16-bit performance counter. All performance counters (except the Receive Framing Error counter and the Transmit Framing Error counter) are inhibited when any of the following alarms occur, and released for operation after the last alarm clears. Loss of Drop Bus J1 pulse (DBLOJ1) when PTEN pin is low. Receive loss of pointer alarm (RLOP) when PTEN pin is high. Receive path AIS alarm (RPAIS) when PTEN pin is high. Loss of Drop Bus Clock (DBLOC). E1 byte AIS Detected (E1AIS) when external alarm enable (EAPE) control bit is 0. External alarm ISTAT pin is high (XISTAT) when external alarm enable (EAPE) control bit is 1. External alarm PAIS pin is high (XPAIS) when external alarm enable (EAPE) control bit is 1. J1 loss of lock (J1LOL) alarm and control bit J1LEN is a 1 (and POHDIS is a 1). J1 trace identifier mismatch (J1TIM) alarm and control bit J1TEN is a 1 (and POHDIS is a 1). Received active low on the external AIS lead (XAIS alarm). Path Signal Label Enable control bit (PSLER) is a 1, and either a PSLERR or C2EQ0 alarm occurs.
The receive framing counters and transmit framing counters are inhibited on loss of frame alignment.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Boundary Scan Introduction
L4M TXC-03456
The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides observability and controllability for the L4M device's interface pins. The Boundary Scan Block consists of a Test Access Port (TAP) controller, instruction and data registers, and a boundary scan path bordering the input and output pins. The boundary scan test bus interface consists of four input signals (Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI) and Test Reset (TRS) and a Test Data Output (TDO) output signal. The TAP controller receives external control information via a Test Clock (TCK) signal and a Test Mode Select (TMS) signal, and sends control signals to the internal scan paths. The scan path architecture consists of a two-bit serial instruction register and two or more serial data registers. The instruction and data registers are connected in parallel between the serial Test Data Input (TDI) and Test Data Output (TDO) signals. The Test Data Input (TDI) signal is routed to both the instruction and data registers and is used to transfer serial data into a register during a scan operation. The Test Data Output (TDO) is selected to send data from either register during a scan operation. When boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the L4M device's internal logic, as illustrated in Figure 24. During boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. A timing diagram for the boundary scan feature is provided in Figure 21. Boundary Scan Support The maximum frequency the L4M device will support for boundary scan is 10 MHz. The L4M device performs the following boundary scan test instructions: - EXTEST - SAMPLE/PRELOAD - BYPASS EXTEST Test Instruction: One of the required boundary scan tests is the external boundary test (EXTEST) instruction. When this instruction is shifted in, the L4M device is forced into an off-line test mode. While in this test mode, the test bus can shift data through the boundary scan registers to control the external L4M input and output leads. SAMPLE/PRELOAD Test Instruction: When the SAMPLE/PRELOAD instruction is shifted in, the L4M device remains fully operational. While in this test mode, L4M input data, and data destined for device outputs, can be captured and shifted out for inspection. The data is captured in response to control signals sent to the TAP controller. BYPASS Test Instruction: When the BYPASS instruction is shifted in, the L4M device remains fully operational. While in this test mode, a scan operation will transfer serial data from the TDI input, through an internal scan cell, to the TDO pin. The purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Figure 24. Boundary Scan Schematic
L4M TXC-03456
Boundary Scan Register
CORE LOGIC OF L4M DEVICE
Signal input and output pins
Instruction Register Bypass Register TAP Controller
TDI
3 Controls IN OUT Boundary Scan Serial Test Data
TDO
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Boundary Scan Chain
L4M TXC-03456
There are 124 scan cells in the L4M boundary scan chain. Bidirectional signals require two scan cells. Additional scan cells are used for direction control as needed. The following table shows the listed order of the scan cells and their function. Scan Cell No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Bidirectional Bidirectional Bidirectional Bidirectional Input Input Input Input Input Input Input Input Input Input Input 120 121 122 123 125 126 127 128 129 131 132 133 134 135 137 Output Output Output Output Output Output 113 114 115 116 117 119 I/O Input Input Output Output Output Output Output Pin No. 104 105 107 108 109 110 111 Symbol TEST EXC1 TOCHC AD0 AD1 AD2 AD3 GZADB AD4 AD5 AD6 AD7 ADD APAR GZBIDA AC1 ACLK ASPE AC1J1 EXTC DC1 DC1J1 DPAR DSPE DCLK TEST DD0 DD1 DD2 DD3
TXC-03456-MB Ed. 1A, January 2000
Comments Should be set to 0.
Output enable for AD0...AD7
Output enable for AC1, ACLK, ASPE, and AC1J1. 0=Output, 1=Input
Should be set to 0.
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DATA SHEET
Scan Cell No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Output Output Output Output Output Output 23 24 25 26 27 29 Bidirectional Input 20 21 Output Output Output Input Input Input 13 14 15 17 18 19 I/O Input Input Input Input Output Input Input Input Input Output Output Output Output Output Output Pin No. 138 139 140 141 143 144 1 2 3 5 6 7 8 9 11 Symbol DD4 DD5 DD6 DD7 PLEQ0 TEST RESET PTEN TEST ROCHC ROCHD RAIPD RPOHD RPOHF RPOHC HIGHZE Should be set to 0. Comments
L4M TXC-03456
HI-Z enable. set to 0 to not tri-state.
GZOSHARED Output enable for PJ. 0=Output, 1=Input PJ CTRL CTRL EXAIS HIGHZ POHDIS GZBDSHARED Output enable for NJ. 0=Output, 1=Input NJ RXCI GZRXCO RXCO AISIND RXD0 RXD1 RXD2 RXD3 GZRXDC Output enable for RXD0...RXD1 Output enable for RXCO.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Scan Cell No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Output Input Input Input Input Input Input Input Input Input Input Input Input Input 51 53 55 56 57 59 60 61 62 63 65 66 67 68 Bidirectional Bidirectional Bidirectional Bidirectional Output 45 47 48 49 50 I/O Output Output Output Output Input Input Input Input Input Bidirectional Bidirectional Bidirectional Bidirectional Pin No. 30 31 32 33 35 36 37 38 39 41 42 43 44 Symbol RXD4 RXD5 RXD6 RXD7 DROPT ENABT ISTAT PAIS STAI D0 D1 D2 D3 GZDUP D4 D5 D6 D7 INT/IRQ GZRDY RDY/DTACK RAMCI SEL RD WR AS MADBUS A0 A1 A2 A3 A4 A5 A6 Output enable for RDY/DTACK Comments
L4M TXC-03456
Output enable for D0...D7. 0=Ouput, 1=Input.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Scan Cell No. 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 Output Output Output Input Input Input Input Input 91 92 93 95 96 97 98 99 I/O Input Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Pin No. 69 71 72 73 74 75 77 78 79 80 81 83 84 85 86 87 89 Symbol A7 AISCK STUFF MOTO NIB TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 EXLOS TEST TXC TEST GZSCAN TEST TPOHF TPOHC TPOHD TAIPD TOCHD TAIPF TAIPC Should be set to 0. Output enable for TESTS. Should be set to 0. Should be set to 0. Comments
L4M TXC-03456
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
EXTERNAL DEVICE OPERATION Phase-Locked Loop
L4M TXC-03456
The phase-locked loop (PLL) circuit for the L4M is shown in Figure 25. The bandwidth (BW Hz) of the PLL is given by the following equation. BW = KdKoKh/2 where, Ko = (30ppm/v) x (139.264 Hz/ppm) x (2) Kd = 5v/[(2) x (256)] Kh = 39/[2 x (15 + 36/2)] = 0.591 The bandwidth of the PLL is equal to 7.7 Hz.
L4M TXC-03456 TTL CTRL
14
0.1 F
39K 36K 15K
2 F
2.2K
CTRL
15
36K
741 +
+2.0V
139.264 MHz VCXO 30 ppm
e.g., Connor-Winfield EDV54-120-31
21
RXCI Termination resistor
TTL
Divided ECL by 4 for Nibble I/O by 8 for Byte I/O
Figure 25. Phase-Locked Loop To ensure that the L4M meets the jitter performance outlined in the ETS1015 document, an adaptive FIFO leak rate algorithm must be employed to dynamically adjust the value written to the FLR register (1AH). An application note on this subject entitled "Jitter Test results for the L4M device - Application Note", document number TXC-03456-0001-AN, Edition 1.0, February 7, 1995 is available upon request.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
140 Mbit/s Line Interface
L4M TXC-03456
Figure 26 is a simplified view of the 140 Mbit/s line interface. The NIB control lead selects whether the receive and transmit line interface is nibble- or byte-wide. The AIS clock (AISCK) should be connected to a stable 34.816 MHz frequency source for nibble interface operation, or to a 17.408 MHz frequency source for byte interface operation. The AIS indication lead (AISIND) provides an external indication when AIS is generated.
L4M TXC-03456 RXDn RXCO
23
Nibble or Byte Data CMI Interface Receive Clock Out Receive Serial Data
RXCI
21
Receive Clock In
CTRL CTRL
14 15
Loop Filter VCXO
AISIND AISCK NIB TXDn
24 71 74
AIS Indication AIS Clock (as required) Nibble/Byte Selection CMI Interface Transmit Serial Data
Nibble or Byte Data
TXC
87
Transmit Clock
Figure 26. L4M 140 Mbit/s Line Interface
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Ring Configuration
L4M TXC-03456
Figure 27 shows two L4M devices arranged in a ring configuration. The two L4Ms exchange path FEBE and RDI information using the alarm indication port. The receive alarm indication port clock and framing pulse are shared with the receive POH byte interface clock and framing pulse signals. This feature is disabled when an active low is placed on the POHDIS lead. Data (RAIPD), as a repetitive byte, is clocked out of the L4M using the path overhead interface clock (RPOHC). The path overhead frame pulse RPOHF indicates the start of the repetitive data byte (RAIPD). In normal operation, receive alarm indication port data (RAIPD) is connected to its mate transmit alarm indication port (TAIPD). The receive clock (RPOHC) is connected to transmit clock TAIPC at its mate, and the receive framing pulse RPOHF is connected to the transmit frame pulse input (TAIPF). Likewise, the mate L4M's receive data is connected to the transmit alarm interface port. The clock present at TAIPC is monitored for operation. An alarm indication port loss of clock alarm causes the FEBE count to be transmitted as 0, and RDI to be transmitted as 0. Writing a 1 to the RING control bit selects the ring mode of operation. The alarm indication byte is sent in the following way: Bits 1-4 B3 Count The byte is repeated nine times. The information sent via the alarm indication port is: - FEBE count - Path RDI/FERF Indication whose value is set by: - Received active low on the external AIS lead (XAIS alarm). - Received E1 byte indication (E1AIS), and control bit EAPE is a 0. - External ISTAT Pin (XISTAT) alarm, when control bit EAPE is a 1. - External PAIS Pin (XPAIS) alarm, when control bit EAPE is a 1. - Drop bus loss of J1 (DBLOJ1) when PTEN is low. - Receive loss of pointer (RLOP) alarm when PTEN is high. - Receive path AIS (RPAIS) alarm when PTEN is high. - Path Signal Label Enable control bit (PSLEN) is a 1, and either a PSLERR or C2EQ0 alarm occurs. - Control bit J1TEN is a 1, and a J1TIM alarm occurs. - Control bit J1LEN is a 1, and a J1LOL alarm occurs. Bit 5 Path RDI 0 Bit 8 0 1
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
L4M TXC-03456
L4M TXC-03456
RAIPD
7
RPOHF RPOHC
9 11
TAIPD
96
TAIPF
98
TAIPC
99
96
98
99
7
9
11
TAIPD
TAIPF
TAIPC
RAIPD
RPOHF RPOHC
L4M TXC-03456
Figure 27. Use of Two L4M Devices in Ring Configuration
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Overhead Communication Channel Interface
L4M TXC-03456
The 139.264 Mbit/s format has ten overhead communication channel bits ("O"-bits) per subframe or 90 bits per frame. The "O"-bit receive and transmit interfaces are treated as an asynchronous serial data communications channel. In the transmit direction, the "O"-bit interface consists of an output clock (TOCHC) and data input lead (TOCHD). Data is clocked into the 140 Mbit/s Mapper on positive transitions of the clock. The clock is non-symmetrical. In the receive direction, the interface consists of an output clock (ROCHC) and data output signal (ROCHD). Data is clocked out of the L4M on negative transitions of the clock. The clock is non-symmetrical. Path Overhead Interface In the transmit direction, timing is provided for clocking in the nine POH bytes. The insertion of POH data from the POH interface is disabled when an active low is placed on the POHDIS lead. When enabled, the transmit POH interface B3 byte position is masked out by the L4M. A B3 test byte may be written by the microprocessor into the L4M RAM and transmitted in place of the calculated B3 byte, or it may function as a B3 error mask. A transmit non-symmetrical clock (TPOHC) and framing pulse (TPOHF) are provided for sourcing the Path Overhead bytes (TPOHD) from the external circuitry. The framing pulse is one clock cycle wide and occurs in the first bit time of the J1 byte. In the receive direction all nine Path Overhead bytes are clocked out at the POH interface. The receive timing is asynchronous in relationship to transmit timing. A receive clock (RPOHC) and framing pulse (RPOHF) are provided for outputting the Path Overhead bytes (RPOHD) for external circuitry. The framing pulse is one clock cycle wide and occurs in the first bit time of the J1 byte.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET MEMORY MAP
L4M TXC-03456
The following definitions are used for the microprocessor access modes of the memory address locations in the tables below: R/W (read/write), R (read only), R(L) (read latched bit position). CONTROL BITS Address (Hex) 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Mode R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TS TS RESETC RESETD RESETS Ts Ts Ts Bit 7 TINVC PSLEN EXZ5 J1COM LFAISE 2048 128 2048 128 Bit 6 TLAIS RDIEN EXZ4 CCITT FDAEN 1024 64 1024 64 Bit 5 RING TRDI EXZ3 Bit 4 EXOB FEBEEN EXH4 J1LEN RPSDS 256 16 256 16 Bit 3 TESTB3 EAPE EXF2 LHZ J1TEN RPSSEL TC1DC 8 RC1DC 8 4 RDI10 4 2 PADS 2 Bit 2 Bit 1 Bit 0 ADDZ RINVC EXJ1 COR SVC4H UPC1 PAISG 1 FEBEBC 1 LOADEN PARDO Ts AC1EN RS BSAISE RS PLDINV
XRDIEN POHEUQ RAISEN EXG1 LLBK TGEN FBTOZ RAISG EXC2 SLBK ANAEN C2FVD
TUNEQ POHRAM TPSSEL 512 32 512 32
EAISEN TCAISEN TOHOUT Transmit C1 Offset
Transmit C1 Offset Receive C1 Offset Receive C1 Offset FIFO Leak Rate Register FIFO Leak Rate Register
Bit 1------------------------------Transmit C1 Value------------------------------Bit 7
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
STATUS BITS Address (Hex) 20 21 22 23 24 25 26 27 28 29 Mode R R(L) R R(L) R R(L) R R(L) R R(L) TLOF TLOF Bit 7 ANOOL ANOOL BUSERR BUSERR TLOC TLOC SINT Bit 6 TLAISD TLAISD RFIFOE RFIFOE ABLOC ABLOC EXTLOS EXTLOS RLOF RLOF Bit 5 TFIFOE TFIFOE RRDI RRDI DBLOC DBLOC AIPLOC AIPLOC TDAI TDAI RDAI RDAI RLOP RLOP Bit 4 ABLOJ1 ABLOJ1 PSLERR PSLERR RLOC RLOC Bit 3 LAISC LAISC C2EQ0 C2EQ0 1SFOU 1SFOU Bit 2 XAIS XAIS J1LOL J1LOL XSTAI XSTAI NEW NEW RPAIS RPAIS Bit 1 DBLOJ1 DBLOJ1 J1TIM J1TIM XISTAT XISTAT
L4M TXC-03456
Bit 0 E1AIS E1AIS RLAISD RLAISD XPAIS XPAIS
INTERRUPT MASK BITS Address (Hex) 30 31 32 33 34 Mode R/W R/W R/W R/W R/W Bit 7 ANOOL BUSERR TLOC HINT TLOF Bit 6 TLAISD RFIFOE ABLOC EXTLOS RLOF Bit 5 TFIFOE RRDI DBLOC AIPLOC TDAI RDAI RLOP Bit 4 ABLOJ1 PSLERR RLOC Bit 3 LAISC C2EQ0 Bit 2 XAIS J1LOL XSTAI NEW RPAIS Bit 1 DBLOJ1 J1TIM XISTAT Bit 0 E1AIS RLAISD XPAIS
TRANSMIT PATH OVERHEAD BYTES Address (Hex) 68 69 6A 6B 6C 6D 6E 6F 80 to BF Mode R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
B3 Test Mask and Test Byte Bit 1-----------------------------------------------------------------------------------------------Bit 8 C2 Signal Label (microprocessor or POH Interface) Bit 1-----------------------------------------------------------------------------------------------Bit 8 Transmit FEBE Count (G1 Byte) Bit 1----------------------------------Bit 4 Transmit RDI Unassigned Bit 6---------------------Bit 8
F2 byte (microprocessor or POH interface) H4 byte (microprocessor or POH interface) Z3 byte (microprocessor or POH interface) Z4 byte (microprocessor or POH interface) Z5 byte (microprocessor or POH interface) J1 Byte (64 or 16 bytes of RAM) Microprocessor or POH interface
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
RECEIVE PATH OVERHEAD BYTES Address (Hex) 75 78 79 7A 7B 7C 7D 7E 7F C0 to FF or C0 to CF F0 to FF R/W Mode R/W R R R R R R R R R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
L4M TXC-03456
Bit 0
C2 Microprocessor-Written Value for Mismatch Bit 1-----------------------------------------------------------------------------------------------Bit 8 B3 Received byte Bit 1-----------------------------------------------------------------------------------------------Bit 8 C2 Received byte Bit 1-----------------------------------------------------------------------------------------------Bit 8 Received FEBE Count (G1 Byte) Bit 1----------------------------------Bit 4 Receive
RDI/FERF
Unassigned Bit 6---------------------Bit 8
F2 byte (microprocessor read) H4 byte (microprocessor read) Z3 byte (microprocessor read) Z4 byte (microprocessor read) Z5 byte (microprocessor read) J1 Byte 64 bytes (or 16 bytes) Received Message Bit 1-----------------------------------------------------------------------------------------------Bit 8 J1 Byte (16 bytes of RAM) J1 Microprocessor Written Value for Mismatch Bit 1-----------------------------------------------------------------------------------------------Bit 8
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
PERFORMANCE COUNTERS Address (Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Mode R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Not Used Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
L4M TXC-03456
Bit 0
B3 counter (low byte) B3 counter (high byte) FEBE counter (low byte) FEBE counter (high byte) Receive analyzer counter (low byte) Receive analyzer counter (high byte) Transmit framing pattern error counter (low byte) Transmit framing pattern error counter (high byte) Receive framing pattern error counter (low byte) Receive framing pattern error counter (high byte) B3 Block Errors (8-bits) Positive Justification Counter (8-bits) Negative Justification Counter (8-bits) NDF Counter Desynchronizer Pointer Offset Counter (PLBOC) PLBOC Sign Bit PLBOC Bit 9
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET MEMORY MAP DESCRIPTIONS
DEVICE IDENTIFIER
L4M TXC-03456
The device identifier (ID) is based on the manufacturer ID found in IEEE standard 1149.1 on Boundary Scan, and the ID assigned by the Solid State Products Engineering Council (JEDEC). The serial format for this ID is shown below: MSB Version 4-bits Part Number 16-bits Manufacturer Identify 11-bits LSB 1
The device identifier is not currently provided as a boundary scan message. However, the manufacturer ID and part number are implemented with read-only capability for microprocessor read access. The manufacturer ID given for all TranSwitch chips is 107 (06B hex.). The part number of the L4M device is 03456 (0D80 hex.) in binary. In addition, the read-only segment is expanded to include a 4-bit mask level field and a 4-bit future growth field as shown below: Address (Hex) 004 003 002 001 000 Mode R R R R R 1 0 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Growth 0 1 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 Bit 0
Mask Level Revision (Version) Level 1 0 1 0 0 0
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
CONTROL REGISTER BIT DESCRIPTIONS Address 10 Bit 7 Symbol TINVC Description
L4M TXC-03456
Transmit Invert Line Clock: A 0 enables byte- or nibble-wide data (TXDn) to be clocked into the L4M on positive transitions of the clock (TXC). A 1 enables byte- or nibble-wide data to be clocked in on negative transitions of the clock. Transmit Line AIS: A 1 enables the L4M to generate and insert an all ones line signal (140 Mbit/s AIS) in the transmit direction, independent of the state of the enable AIS bits and alarms. Transmit line AIS is generated under the following conditions: - External loss of signal alarm (EXTLOS) when EAISEN is a 1, - Loss of transmit clock alarm (TLOC) when TCAISEN is a 1, - Loss of 140 Mbit/s frame alignment when LFAISE is a 1, - Microprocessor writes a 1 to this bit position.
6
TLAIS
5
RING
Path Protected Ring Mode: The L4M must be connected to a mate L4M for this mode. A 1 enables the Transmit Alarm Indication Port to control the FEBE (when FEBEEN=1) and RDI (when RDIEN=1) that are transmitted in the G1 byte. External "O"-bit Interface: A 1 enables the Overhead Communication Channel data interface for transmitting the 90 overhead communication channel bits ("O"-bits) specified in the 140 Mbit/s SDH/SONET format. The interface bits are inserted asynchronously into the SDH/SONET format with respect to the nine subframes. A 0 causes zeros to be transmitted for all of the "O"-bits. Test B3 Byte: A 1 enables a microprocessor-written byte (location 68H) to be the transmitted B3 byte. A 0 enables the microprocessor-written byte in location 68H to work as a B3 error mask. A 1 written into one or more bit positions will cause that bit position to be transmitted inverted from its calculated value, until the bit position is written with a 0. External RDI Enable: A 1 in this bit and the RDIEN bit enables a path RDI (bit 5 in G1) to be generated and transmitted when a high is placed on the STAI pin. A 0 disables the logic level placed on the STAI pin from controlling the state of path RDI. POH Bytes Enabled During Unequipped Status: This bit works in conjunction with control bit TUNEQ for generating an unequipped channel. The Path Overhead Byte enable feature must be enabled (POHDIS lead is high). TUNEQ 0 1 1 POHEUQ Action X Normal Operation 0 Unequipped Channel. POH and payload bytes are transmitted as 0. 1 Supervisory Unequipped Channel. POH enabled. Payload bytes transmitted as 0.
4
EXOB
3
TESTB3
2
XRDIEN
1
POHEUQ
- 67 -
TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 10 Bit 0 Symbol ADDZ Description
L4M TXC-03456
Add Bus Force High Impedance State: Works in conjunction with the control bit FBTOZ for controlling the add bus signal states. Assuming that there is no drop or add bus alarms, the following states are possible: ADDZ 0 0 1 FBTOZ 0 1 0 Action Normal operation. Unused bytes (TOH and POH bytes when disabled) are transmitted in the high impedance state. Normal operation. Unused bytes (TOH and POH bytes when disabled) are transmitted as 0s. ADD is forced to 0. All add bus bytes (time slots) forced to the high impedance state. Note: when add bus timing is selected, data only will be forced to the high impedance state. The C1J1 and SPE signals are inputs. In the other two timing modes, add bus and external timing modes, the add bus clock (ACLK), SPE indicator, C1J1 will be forced to 0. ADD is forced to 1. All add bus Bytes (time slots) forced to the zero state. Note: when add bus timing is selected, data only will be forced to the zero state. The C1J1 and SPE signals are inputs. In the other two timing modes, add and external, the add bus clock, SPE, C1J1 will be forced to 0. ADD is forced to 0.
1
1
When there is an alarm for the clock that sources the add bus data, the operation in the table below occurs:
Action for Timing Modes ADDZ 0 FBTOZ 0 ADD Bus Add Bus data forced to Hi-Z state. ADD=1. DROP Bus Add Bus data is forced to its Hi-Z state. ASPE, ACLK, AC1J1 forced to 0. ADD=1. External Add Bus data is forced to its Hi-Z state. ASPE, ACLK, AC1J1 forced to 0. ADD=1. Add Bus data is forced to 0 state. ASPE, AC1J1, ACLK, ADD are forced to 0 state. Add Bus data is forced to Hi-Z state. ASPE, ACLK, AC1J1 forced to 0. ADD=1. Add Bus data is forced to 0 state. ACLK, ASPE, AC1J1, and ADD are forced to 0.
0
1
Add Bus data is Add Bus data forced to 0 state. forced to 0 state. ASPE, AC1J1, ACLK, ADD=0. ADD are forced to 0 state. Add Bus data is Add Bus data is forced to Hi-Z state. forced to Hi-Z ASPE, ACLK, AC1J1 state. ADD=1. forced to 0. ADD=1. Add Bus data and ADD are forced to the 0 state. Add Bus data is forced to 0 state. ACLK, ASPE, AC1J1, and ADD are forced to 0.
1
0
1
1
- 68 -
TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 11 Bit 7 Symbol PSLEN Description
L4M TXC-03456
Path Signal Label Alarm Enable: A 1 enables a 140 Mbit/s receive line AIS, and path RDI to be generated and sent when a C2 mismatch alarm (PLSERR) or unequipped (C2EQ0) alarm occurs. Far End Receive Failure Enable: A 1 enables the internal alarms to determine the state of the transmitted RDI bit, while a 0 disables the internal alarms from controlling the state of the RDI bit. When written with a 0, the microprocessor must write the state of the RDI bit by writing a 1 or 0 to control bit TRDI or bit 3 in the G1 POH byte register location 7AH. The following table is a summary of the various conditions that generates an RDI. - External G1 byte, when EXG1 is a 1 - RDIEN is a 1 and RING and EXG1 are 0: - DBLOC alarm=1 and DROPT pin is low - Low on EXAIS (pin 17) - E1 byte AIS indication, when EAPE is a 0 - High on ISTAT (pin 37), when EAPE is a 1 - High on PAIS (pin 38), when EAPE is a 1 - High on STAI (pin 39), when XRDIEN is a 1 - Drop bus loss of J1 alarm (DBLOJ1) when PTEN (pin 2) is low - Path signal label mismatch (PSLERR), when PSLEN is a 1 - Unequipped status (C2EQ0), when PSLEN is a 1 - J1 loss of lock (J1LOL), when J1LEN is a 1 - J1 trace message mismatch (J1TIM), when J1TEN is a 1 - Loss of pointer (RLOP), when PTEN (pin 2) is high - Path AIS (RPAIS), when PTEN (pin 2) is high. - RING and RDIEN are a 1, and EXG1 is 0: - RDI status via Alarm Indication Port (no AIPLOC alarm). - RDIEN and EXG1 are 0: - Bit 3 in 6AH is a 1 (transmit G1 byte in RAM). - TRDI is a 1.
6
RDIEN
5
TRDI
Transmit RDI: A 1 generates an RDI (Bit 5 in the transmit G1 byte is set to 1) when control bit RDIEN bit is 0. This bit is orred with the microprocessor-written RAM G1 value for RDI (bit 3) in location 6AH. Far End Block Error Enable: A 1 enables the received B3 value to generate the transmitted FEBE count. A 0 enables a microprocessor-written value (bits 7 - 4 in register location 6AH) to be transmitted as the FEBE count. The FEBE count is sent under the following conditions: - Via external G1 byte, when EXG1 is a 1. - Microprocessor-written value in bits 7-4 in 6AH, when FEBEEN is a 0. - Received B3 BIP-8 errors, when FEBEEN is a 1, and RING and EXG1 are 0. - Received B3 BIP-8 errors via Alarm Indication Port, when FEBEEN and RING are 1, and EXG1 is 0.
4
FEBEEN
- 69 -
TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 11 Bit 3 Symbol EAPE Description
L4M TXC-03456
External Alarm Pin Enable: A 1 enables the external ISTAT (pin 37) and PAIS (38) pins to function in place of the E1 byte AIS detection circuit (out of band AIS indication). A 0 disables the external alarm pins and enables the E1 byte AIS detection circuit (in band AIS indication). The E1 byte may be used to carry an in band upstream AIS indication. The E1 byte AIS detection circuitry uses majority logic to determine if the byte is carrying an AIS indication. Receive Line AIS Enable: A 1 enables internal (and external) alarms to generate a receive 140 Mbit/s line AIS. A 0 disables the ability of the internal alarms to generate a 140 Mbit/s line AIS. The following table is a summary of the various conditions that generates a 140 Mbit/s line AIS, and provides an AIS indication (pin 24). - RAISEN is a 1: - Low on EXAIS (pin 17) - E1 byte AIS indication, when EAPE is a 0 - High on ISTAT (pin 37), when EAPE is a 1 - High on PAIS (pin 38), when EAPE is a 1 - Drop bus loss of J1 alarm (DBLOJ1) when PTEN (pin 2) is low - Drop bus loss of clock (DBLOC), when BSAISE is a 0 - Path signal label mismatch (PSLERR), when PSLEN is a 1 - Unequipped status (C2EQ0), when PSLEN is a 1 - J1 loss of lock (J1LOL), when J1LEN is a 1 - J1 trace message mismatch (J1TIM), when J1TEN is a 1 - Loss of pointer (RLOP), when PTEN (pin 2) is high - Path AIS (RPAIS), when PTEN (pin 2) is high. - RAISEN is a 0: - The microprocessor writes a 1 to RAISG. Note. The microprocessor may write to control bit RAISG at any time to generate a line AIS. However, writing a 0 to RAISEN prevents contention between the internal alarms and the microprocessor for generation of line AIS. - Receive loss of line frame alignment (RLOF), when LFAISE is a 1 and BSAISE is a 0.
2
RAISEN
1
RAISG
Generate Receive AIS: A 1 causes a receive 140 Mbit/s line AIS to be generated independent of the internal alarms. Note: The microprocessor may write to control bit RAISG at any time for generating a line AIS. However, writing a 0 to RAISEN prevents contention between the internal alarms and the microprocessor for generation of line AIS. Receive Invert Line Clock: Byte- or nibble-wide data is clocked out of the L4M on negative transitions of the clock (RXCO) when this bit is a 0. A 1 enables the byte or nibble line signal to be clocked out of the L4M on positive transitions of the clock.
0
RINVC
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 12 Bit 7 Symbol EXZ5 Description
L4M TXC-03456
Transmit External Z5 Byte: A 1 enables the Z5 byte from the external POH interface to be transmitted. A 0 enables the microprocessor-written value in register location 6FH to be transmitted. Transmit External Z4 Byte: A 1 enables the Z4 byte from the external POH interface to be transmitted. A 0 enables the microprocessor-written value in register location 6EH to be transmitted. Transmit External Z3 Byte: A 1 enables the Z3 byte from the external POH interface to be transmitted. A 0 enables the microprocessor-written value in register location 6DH to be transmitted. Transmit External H4 Byte: A 1 enables the H4 byte from the external POH interface to be transmitted. A 0 enables the microprocessor-written value in register location 6CH to be transmitted. Transmit External F2 Byte: A 1 enables the F2 byte from the external POH interface to be transmitted. A 0 enables the microprocessor-written value in register location 6BH to be transmitted. Transmit External G1 Byte: A 1 enables the G1 byte from the external POH interface to be transmitted. A 0 selects the states of the G1 byte to be written by internal logic, or by the microprocessor, as enabled. Transmit External C2 Byte: A 1 enables the C2 byte from the external POH interface to be transmitted. A 0 enables the microprocessor-written value in register location 69H to be transmitted. Transmit External J1 Byte: A 1enables the J1 byte from the external POH interface to be transmitted. A 0 enables the microprocessor-written value to be transmitted. J1 Message Comparison Mode: Works in conjunction with the CCITT control bit according to the following table: CCITT 0 J1COM X Action Transmit and receive J1 memory segments are configured for 64 bytes. Incoming messages are written in a rotating fashion with no defined starting address. Transmit and receive J1 memory segments are configured for 16 bytes. Incoming messages are written in a rotating fashion with no defined starting address. Transmit and receive J1 memory segments are configured for 16 bytes. J1 incoming message comparison feature enabled. The microprocessor writes the expected 16-byte message into RAM. After multiframe alignment is established, the J1 bytes in the message are compared against the microprocessor-written bytes, located in register location F0 to FFH.
6
EXZ4
5
EXZ3
4
EXH4
3
EXF2
2
EXG1
1
EXC2
0
EXJ1
13
7
J1COM
1
0
1
1
6
CCITT
J1 Memory Size: A 1 dimensions the transmit and receive memory segment size to 16 bytes, while a 0 dimensions the memory segment to 64 bytes.
TXC-03456-MB Ed. 1A, January 2000
- 71 -
DATA SHEET
Address 13 Bit 5 Symbol TUNEQ Description
L4M TXC-03456
Transmit Unequipped Status: This bit works in conjunction with control bit POHEUQ for generating an unequipped channel. The Path Overhead Byte enable feature must be enabled (POHDIS lead is high). TUNEQ 0 1 1 POHEUQ Action X Normal Operation 0 Unequipped Channel. POH and payload bytes are transmitted as 0. 1 Supervisory Unequipped Channel. POH bytes enabled. Payload bytes transmitted as 0.
4
POHRAM
Path Overhead Bytes to RAM: A 1 enables the transmit POH bytes (e.g. EXH4 is equal to 1) from the external POH interface to be written into RAM prior to transmission. A 0 still enables selected external interface POH bytes to be transmitted, but the RAM locations are not written with the value of the external POH byte. Instead, the RAM locations will hold the microprocessor-written values. Force Receive Line to High Impedance: A 1 forces the receive byte or nibble data (RXDn), and line output clock (RXCO) to a high impedance state, until this bit is written with a 0. This bit is set to 1 after a device reset. Line Loopback: A 1 written into this location enables the received line signal to be looped back as the transmit line signal. The received data and clock are provided at either the byte or nibble receive line interfaces. SDH/SONET Loopback: A 1 written into this location enables a VC-4/ SPE loopback. This feature is not valid when the PTEN pin is set to 1. Non-Saturating Performance Counters Enable: A 1 enables the performance counters to be non-saturating with roll over capability. A 0 causes all performance counters to be saturating, stopping at their maximum value, with clear on read capability. External Loss Of Signal AIS Enable: A 1 enables a 140 Mbit/s AIS to be transmitted when a low is applied to EXLOS (pin 85). A 0 disables an external loss of signal indication from transmitting an AIS. Transmit Loss of Clock AIS Enable: A 1 enables the L4M to send a 140 Mbit/s AIS when a transmit loss of clock alarm (TLOC) is detected. A 0 disables a transmit loss of clock alarm (TLOC) from transmitting an AIS.
3
LHZ
2
LLBK
1 0
SLBK COR
14
7
EAISEN
6
TCAISEN
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 14 Bit 5 Symbol TOHOUT Description
L4M TXC-03456
Transport Overhead Bytes Output Enabled: A 1 enables the L4M to generate the three A1 and A2 framing bytes, the C1 byte, and the H1 and H2 bytes, according to the following table. This feature in enabled in the drop bus and external timing modes only. TOHOUT UPC1 SVC4H 0 X 0 Action No TOH bytes. The SPE starting location (starting with J1) equals 522 when drop or the external timing mode is selected. For add bus timing, the starting location is determined by the J1 pulse (AC1J1). No TOH bytes. The SPE starting location (starting with J1) equals 0 when drop or the external timing mode is selected. For add bus timing, the starting location is determined by the J1 pulse (AC1J1). A1, A2, C11, and H1/H2 byte generated. The C11 byte (first C1 byte) is fixed as 01H. The pointer value is equal to 522, the starting location of the SPE. The generation of the TOH bytes is disabled in the add bus timing mode. A1, A2, C11, and H1/H2 byte generated. The C11 byte (first C1 byte) is fixed as 01H. The pointer value is equal to 0, the starting location of the SPE. The generation of the TOH bytes is disabled in the add bus timing mode. A1, A2, C11, and H1/H2 byte generated. The C11 byte (first C1 byte) is the microprocessor-written value (location 1EH). The pointer value is equal to 522, the starting location of the SPE. The generation of the TOH bytes is disabled in the add bus timing mode. A1, A2, C11, and H1/H2 byte generated. The C11 byte (first C1 byte) is the microprocessor-written value (location 1EH). The pointer value is equal to 0, the starting location of the SPE. The generation of the TOH bytes is disabled in the add bus timing mode.
0
X
1
1
0
0
1
0
1
1
1
0
1
1
1
4
J1LEN
J1 Loss Of Lock Alarm Action Enable: A 1 enables the L4M to generate a receive 140 Mbit/s AIS (when AIS is enabled; RAISEN is a 1), and path RDI is enabled and the L4M is not in a path protection ring configuration (when RDIEN is a 1 and RING is 0) when a J1 loss of lock is detected.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 14 Bit 3 Symbol J1TEN Description
L4M TXC-03456
J1 Trace Identifier Mismatch Alarm Action Enable: A 1 enables the L4M to generate a receive 140 Mbit/s AIS (when AIS is enabled; RAISEN is a 1), and path RDI is enabled and the L4M is not in a path protection ring configuration (when RDIEN is a 1 and RING is 0) when a J1 a trace identifier mismatch is detected. Transmit Test Generator Enable: A 1 enables the transmit 223-1 test pseudo random generator. The transmit clock signal (TXC) must be present. Byte or nibble interface data is disabled. Test Analyzer Enable: A 1 enables the 223-1 pseudo random test analyzer. The test analyzer samples the receive data. Errors are counted in a 16-bit performance counter after alignment is established. Start Transmit VC-4 after H3 Byte: This feature is operational in the drop timing and external timing modes only. A 1 enables the VC-4 (starting with the J1 byte) to start after the H3 byte. The H1/H2 pointer value is set to 0 when the TOH feature is enabled (TOHOUT is a 1). A 0 enables the VC-4 to start after the C1 byte with a pointer value equal to 522. In the add bus timing mode, an add bus J1 pulse (in AC1J1) determines the starting location of the SPE. Loss Of Frame AIS Enable: A common control bit for both the receive and transmit performance monitoring circuits. A 1 enables a receive or transmit loss of frame alarm to generate a receive or transmit 140 Mbit/s AIS. The generation of AIS in the receive direction is disabled when the bit stuffing AIS feature is enabled (BSAISE is a 1). A 0 disables a loss of frame alarm from generating AIS. Frame Alignment AIS Enable: A 1 enables frame alignment to work in conjunction with the AIS detector. The AIS detection occurs when AIS is detected and loss of frame has occurred. AIS recovery occurs when frame alignment occurs or the AIS condition goes away. A 0 disables the frame alignment from working with the AIS detection circuit, that is, AIS can be declared even if a loss of frame condition is not present. Transmit Pointer S-bit Select: Enabled when control bit TOHOUT is a 1 in the drop bus and external timing modes. A 1 permits the microprocessor to write the value of the transmit S-bits in the H11, H12, and H13 bytes. A 0, forces the S-bits in H11 to be sent as 10, and the S-bits in H12 and H13 to be sent as 00. See register 1DH. Receive Pointer S-bit Disabled: Enabled when PTEN (pin 2) is high enabling the pointer tracking machine. This bit also works in conjunction with the RPSSEL bit according to the following table. RPSDS 0 0 1 RPSSEL Action 0 Pointer byte H11 S-bits are checked in pointer tracking machine against the value 10. 1 Pointer byte H11 S-bits are checked in pointer tracking machine against a microprocessor-written value in bits 1 and 0 in 1DH. X The S-bit check is disabled in the pointer tracking machine.
2
TGEN
1
ANAEN
0
SVC4H
15
7
LFAISE
6
FDAEN
5
TPSSEL
4
RPSDS
- 74 -
TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 15 Bit 3 Symbol RPSSEL Description
L4M TXC-03456
Receive Pointer S-Bit Select: Enabled when PTEN (pin 2) is high enabling the pointer tracking machine. This bit works in conjunction with the RPSDS bit according to the table given above. Force Unused Bytes To Zero: A 1 forces the unused TOH bytes and POH bytes (when disabled) to 0. A 0 forces the unused bytes to a high impedance state. C2 Fixed Value Disabled: A 1 disables the comparison of the received C2 byte against the fixed hardware value of 01H in the C2 mismatch detection circuit. The C2 mismatch comparison is performed against the microprocessor-written value only. Microprocessor Writes C1 Value: Enabled when control bit TOHOUT is a 1 in the drop bus and external timing modes. A 1 enables the microprocessor to write the value of the transmitted C1 byte. A 0 generates the value of 01H for the transmitted C1 byte. Transmit C1 Offset Register: Enabled in the external timing mode only, when a high is placed on ENABT (pin 36), and when control bit TC1DC is a 1. The 12-bit register location compensates for the position of the C1 pulse in the EXC1 signal (pin 105). The LSB is bit 0 in 17H, and the MSB is bit 7 in 16H. The register compensates for up to 2429 (270 columns X 9 rows - 1). For example, if the C1 pulse is in the correct position, zeros are written to the register. The correct position of the framing reference is when C1 corresponds to the C11 position in the SDH/SONET format. When a binary 1 is written to the register (bit 0 in 17H is a 1), it is assumed that the position of the C1 pulse present in the EXC1 signal is shifted in time one byte and the input pulse corresponds to the C12 byte position in the SDH/SONET frame. This means that the starting point for the frame should be one byte earlier. Values written into the register greater than a binary value of 2429 will be counted as zero delay. Transmit C1 Delay Control: Enabled in the external timing mode only, when a high is placed on ENABT (pin 36). A 1 enables the transmit 12-bit C1 offset register in locations 16H and 17H to compensate for a C1 offset delay in the transmit direction. Path AIS Generator Enable: A 1 causes path AIS to be generated in the transmit direction. The transmitted payload and POH bytes are forced to the 1 state (if POHDIS=1), in addition to the TOH bytes (when enabled).
2
FBTOZ
1
C2FVD
0
UPC1
16 17
7-4 7-0
Transmit C1 Offset
16
3
TC1DC
0
PAISG
- 75 -
TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 18 19 Bit 7-4 7-0 Symbol Receive C1 Offset Description
L4M TXC-03456
Receive C1 Offset Register: Enabled when a high is placed on the pointer tracking machine control lead PTEN (pin 2), and when control bit RC1DC is a 1. The 12-bit register location compensates the position of the C1 pulse in the DC1J1 or DC1 signal (pin 127, 126). The LSB is bit 0 in 19H, and the MSB is bit 7 in 18H. The register compensates for up to 2429 (270 columns X 9 rows - 1). For example, if the C1 pulse is in the correct position, zeros are written to the register. The correct position of the framing reference is when C1 corresponds to the C11 position in the SDH/SONET format. When a binary 1 is written to the register (bit 0 in 19H is a 1), it is assumed that the position of the C1 pulse present in the DC1 signal is shifted in time one byte and the input pulse corresponds to the C12 byte position in the SDH/SONET frame. This means that the starting point for the frame should be one byte earlier. Values written into the register greater than a binary value of 2429 will be counted as zero delay. Receive C1 Delay Control: Enabled when the pointer tacking machine is selected, when a high is placed on PTEN (pin 2). A 1 enables the receive 12-bit register in locations 18 and 19H to compensate for a C1 offset delay in the receive direction. RDI/FERF Recovery/Detection 10 Consecutive Enable: A 1 selects 10 consecutive events as the value for detection and recovery. A 0 selects 5 consecutive events as the value for detection and recovery. Pointer Tracking Machine AIS to LOP Transition Disabled: A 1 disables the AIS to LOP transition in the pointer tracking state machine. A 0 enables the AIS to LOP transition in the pointer tracking machine. FEBE Block Count Enable: A 1 enables the FEBE counter to be configured to count FEBE blocks instead of FEBES. A valid count (between 1 and 8) will increment the 16-bit counter once. A 0 configures the FEBE counter to count FEBES.
18
3
RC1DC
2
RDI10
1
PADS
0
FEBEBC
1A 1B
7-0 7-1
Pointer Leak FIFO Leak Rate Register: The 15-bit value written into registers 1A and 1BH is used for presetting the internal pointer leak counter. The value Rate Register written into this register is based on the rate of occurrence of pointer movements from the number of counts read from positive/negative stuff counters, and the NJ/PJ indication pins. This count will represent the average leak rate. A count of 1 will decrement the pointer leak counter every three rows. Thus the minimum time to leak out one pointer movement is 8 frames or 1 millisecond, since each pointer movement is 24 bits. Bit 7 in register 1BH is assigned as the MSB, and represents bit 15 in the string, as shown below: | Bit 7 Register 1B 5432 | 1 7 Register 1A 6 54 3 | 2 1 0
6
A pin (PLEQ0) is provided that will give a positive indication when the pointer leak counter is equal to zero. This indication is reset to zero when the pointer leak counter is preset. Register 1AH is preset to 01H after a device reset.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 1B Bit 0 Symbol LOADEN Description
L4M TXC-03456
Load Enable: Used for desynchronizer operation. The internal pointer leak counter shall be preset with the 15-bit leak rate value using the following steps: 1. Write the value to the seven upper bits (with 7 being the MSB), and a 0 to this bit. 2. Write the 8-bit value into the lower register (1A). 3. Write a 1 to this bit, or write the seven upper bits in this register, along with a 1 to this bit. The internal counter will preset with the 15-bit value on the 0 to 1 transition. This bit is set to 1 after a device reset.
1C
7
RESETC
Reset Counters: A 1 causes the performance counters to reset. When the reset is completed, this bit is self clearing and this bit position becomes a 0. Reset Mapper: A 1 resets the Mapper. The Mapper will remain reset until the processor writes a 0 into this location. Reset Desynchronizer: A 1 resets the two FIFOs in the desynchronizer to mid-range values. Parity Data Byte Only: A common bit for both the drop and add buses, and valid for all timing modes. A 1 enables parity to be calculated for data bytes only. A 0 enables parity to be calculated for the add bus output signals, and drop bus input signals. Add Bus C1 Pulse Enable: A 1 enables the C1 pulse to be transmitted as a separate signal instead of in the AC1J1 signal in the external and drop timing modes. A 0 enables the AC1J1 signal to carry both the C1 and J1 signals. In the add bus timing mode, the C1 signal can be applied on the AC1 pin instead of in the C1J1 signal independent of the state of this bit. Bit Stuffing AIS Enable: A 1 causes an internal bit stuffing implementation to be used for the transmit and receive 140 Mbit/s line AIS generation instead of using the external AIS clock. This bit is set to 0 upon power-up (selecting the external AIS clock). When the bit stuffing AIS feature is selected, the receive performance monitor circuit and AIS detection circuits are disabled when receive AIS is generated automatically by the L4M. Please note that the loss of the drop bus clock will disable the generation of receive AIS based on bit stuffing.
6 5 2
RESETD RESETS PARDO
1
AC1EN
0
BSAISE
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 1D Bit 7-0 Symbol Description
L4M TXC-03456
Pointer S-bit Microprocessor-Written Values: The bits in this location S-Bits P Control are the microprocessor-written S-bits in the transmit pointer bytes, and the S-bits used in the receive pointer tracking machine. The transmit S-bits in this location are enabled when control bits TPSSEL and TOHOUT are 1. In the receive direction, the S-bits in this location are enabled when control bit RPSSEL is 1 and RPSDS is 0. The bits are defined as: Bit 7 is the S-bit state in bit 5 in the transmitted H11 byte. Bit 6 is the S-bit state in bit 6 in the transmitted H11 byte. Bit 5 is the S-bit state in bit 5 in the transmitted H12 byte. Bit 4 is the S-bit state in bit 6 in the transmitted H12 byte. Bit 3 is the S-bit state in bit 5 in the transmitted H13 byte. Bit 2 is the S-bit state in bit 6 in the transmitted H13 byte. Bit 1 is the S-bit state used to compare bit 5 in the received H11 byte in the pointer state machine. Bit 0 is the S-bit state used to compare bit 6 in the received H11 byte in the pointer state machine.
1E
7-0
C1
C1 Microprocessor-Written Value: When control bits TOHOUT and UPC1 are equal to 1, the transmitted C1 value is the value written into this location by the microprocessor. When control bit TOHOUT is a 1 and UPC1 is a 0, a fixed value of 01H is transmitted, and this register location is disabled. Phase-Locked Loop Detector Invert Control Bit: A 1 inverts the sense of one of the phase-locked loop internal phase detector's inputs. This bit should be set to 1 for normal operation.
1F
0
PLDINV
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
STATUS REGISTER BIT DESCRIPTIONS
L4M TXC-03456
The unlatched alarms are allocated to even numbered hexadecimal address locations, while the latched alarm bit positions are allocated to odd numbered register locations. A latched bit sets on the positive level of the alarm. A latched bit position clears on a microprocessor read cycle. If the alarm is active after the read cycle, the bit position will relatch. Address 20 21 Bit 7 Symbol ANOOL Description Analyzer Out Of Lock: When enabled, an alarm occurs when the 223-1 analyzer is out of lock. An out of lock alarm occurs when 30 bits in a 1000 bits are received in error. In lock occurs when the first 24 bits in the pattern are received correctly. An out of lock disables the analyzer error 16-bit counter. This bit is forced to 0 when the ANAEN control bit is set to 0. Transmit Line AIS Detected: An alarm occurs when a 140 Mbit/s AIS has been detected (all ones in the transmit bit stream). When control bit FDAEN is a 0, an AIS is detected when the incoming signal has five or less zeros in each of two consecutive frame periods (2928 bits per frame). Recovery occurs when if each of two consecutive frame periods contains six or more zeros. When control bit FDAEN is a 1, AIS is detected when the incoming signal has five or less zeros in each of two consecutive frame periods, and a loss of frame alignment has been detected. Recovery occurs when each of two consecutive frame periods contains six or more zeros, or frame alignment has occurred. Other than reporting the alarm, no action is taken. Transmit FIFO Error Detected: An alarm occurs when an overflow or underflow condition has taken place in the transmit FIFO. The FIFO recenters automatically after the FIFO error. Other than reporting the alarm, and recentering the FIFO, no action is taken. Add Bus Loss of J1: An alarm occurs when, in add bus timing mode, the J1 pulse in the AC1J1 signal is missing for 8 consecutive frames. Recovery occurs when the J1 pulse in the AC1J1 signal is present for 8 consecutive frames. Loss of AIS Clock: An alarm occurs when the AIS input clock (AISCK) is stuck high or low for 12-34 consecutive clock cycles of the RAM clock (RAMCI). Recovery occurs on the first clock transition. This clock is used to generate the 140 Mbit/s line AIS when control bit BSAISE is a 0. External AIS Indication: An indication occurs when an active low is present on the EXAIS pin. When control bit RAISEN is a 1, a receive 140 Mbit/s AIS is generated, and a path RDI is generated when RDIEN=1. Drop Bus Loss of J1: An alarm occurs when the J1 pulse in the DC1J1 signal is missing for 8 consecutive frames. Recovery occurs when the J1 pulse in the DC1J1 pulse is present for 8 consecutive frames. When the pointer tracking feature is enabled (PTEN is high), the detection of this alarm is disabled. AIS Detected in the E1 Byte: An alarm occurs when a majority of all ones (5 out of 8 bits are a 1) has been detected in the incoming E1 byte once. Recovery occurs when a majority of ones is not detected once. This provides a means of signaling the 140 Mbit/s Mapper that an upstream SDH/SONET Loss Of Frame and other alarms have occurred.
6
TLAISD
5
TFIFOE
4
ABLOJ1
3
LAISC
2
XAIS
1
DBLOJ1
0
E1AIS
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 22 23 Bit 7 Symbol Description
L4M TXC-03456
BUSERR Received Parity Error Detected: An alarm indicates that a parity error has been detected in the drop bus signals. The drop bus data, SPE signal and composite C1J1 pulse are calculated for odd parity and compared against the parity bit input for parity errors when the pointer tracking feature is disabled (PTEN lead is low). The drop bus data, and C1 pulse is calculated for odd parity and compared against the parity bit input for parity errors when the pointer tracking feature is enabled (PTEN lead is high). When a 1 is written to control bit PARDO, the parity calculation and comparison is for the data byte only regardless of the state of the PTEN lead. No other action is taken, other than the alarm indication. RFIFOE Receive FIFO Error: An alarm occurs when the receive second stage FIFO in the desynchronizer has either underflowed or overflowed. The FIFO is recentered automatically. No other action is taken. Receive RDI Alarm Detected: An alarm occurs when a path RDI alarm has been detected in bit 5 of the received G1 byte. Control bit RDI10 determines whether the consecutive event requirement for detection and recovery is 5 or 10.
6
5
RRDI
4
PSLERR Path Signal Label Mismatch Detected: An alarm indicates that the received C2 byte did not match the microprocessor-written value in location 75H, nor did it match the internal 01H value (when control bit C2FVD is a 0) for 5 consecutive frames. Recovery occurs when a match occurs in the C2 comparison byte (75H) or internal 01H value (when enabled), for 5 consecutive frames. When control bit C2FVD is a 1, the comparison against the internal 01H value is disabled. This alarm is disabled if a C2 unequipped alarm occurs. C2EQ0 C2 Byte Equal to Zero: An alarm occurs when the received C2 byte is all zeros for 5 consecutive frames, indicating that the VC-4/SPE is carrying an unequipped channel status (POH bytes and payload bytes are equal to zero). Recovery occurs when the received C2 byte is not all zeros for 5 consecutive frames. J1 Loss of Lock Alarm: An alarm occurs when the alignment of the J1 trace identifier label (message) has not been established. The J1 detection circuit is enabled when control bits J1COM and CCITT are a 1. The J1LOL alarm will become momentarily active when the following alarms are exited: DBLOJ1 when PTEN pin is low; E1AIS when EAPE bit is 0; XPAIS or XISTAT when EAPE bit is 1; RLOP or RPAIS when PTEN pin is high. J1 Trace Identifier Mismatch: An alarm indicates that the received stable 16-byte message did not match for one message time. Recovery from this alarm occurs when the J1 state machine losses lock (J1LOL) and then acquires lock with a 16-byte stable J1 message that matches the J1 comparison message in registers F0H to FFH.
3
2
J1LOL
1
J1TIM
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 22 23 Bit 0 Symbol RLAISD Description
L4M TXC-03456
Receive Line AIS Detected: The alarm detection is enabled when control bit BSAISE is a 0 (bit stuffing AIS disabled), or when BSAISE=1 and the L4M is not generating a receive AIS based upon received alarms. When control bit FDAEN is a 0, a 140 Mbit/s line AIS is detected when the receive line signal (after the desynchronizer) has five or less zeros in two consecutive frame periods. Recovery occurs if each of the two consecutive frame periods has six or more zeros. When control bit FDAEN is a 1, an alarm occurs when the receive line signal has five or less zeros in two consecutive periods, and loss of frame has occurred. Recovery occurs if each of two consecutive frame periods has six or more zeros, or frame alignment has been detected. Transmit Loss Of Clock: An alarm occurs when the transmit line clock (TXC) is stuck high or low for 13-34 or more consecutive clock cycles of the RAM clock (RAMCI). Recovery occurs on the first clock transition. Add Bus Loss Of Clock: An alarm occurs when the add bus input clock (ACLK) in the add bus timing mode is stuck high or low for 13-34 or more consecutive clock cycles of the RAM clock (RAMCI). Recovery occurs on the first clock transition. Drop Bus Loss Of Clock: An alarm occurs when the drop bus input clock (DCLK) is stuck high or low for 13-34 or more consecutive clock cycles of the RAM clock (RAMCI). Recovery occurs on the first clock transition. Receive Line Loss Of Clock: An alarm occurs when the receive line input clock (RXCI) is stuck high or low for 12-35 or more consecutive clock cycles of the RAM clock (RAMCI). Recovery occurs on the first clock transition. First Stage FIFO Overflow or Underflow: An alarm occurs when the 1st stage receive FIFO in the desynchronizer has either underflowed or overflowed. The FIFO is recentered automatically. No other action is taken. The 1st stage FIFO will overflow or underflow if the value in register 1AH and 1BH is too large, such that the pointer movements are not leaked out as fast as they are arriving. SDH/SONET Network Alarm Indication: An indication occurs when an active high is present on the STAI pin. When control bits XRDIEN and RDIEN are set to 1, a path RDI is transmitted for the duration of the alarm. External SDH/SONET Alarm: An indication occurs when an active high is present on the ISTAT pin. When control bit EAPE is a 1, path RDI is transmitted and a receive AIS is generated for the duration of the alarm. External Path AIS Alarm: An indication occurs when an active high is present on the PAIS pin. When control bit EAPE is a 1, path RDI is transmitted and a receive AIS is generated for the duration of the alarm.
24 25
7
TLOC
6
ABLOC
5
DBLOC
4
RLOC
3
1SFOU
2
XSTAI
1
XISTAT
0
XPAIS
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 26 Bit 7 Symbol SINT Description
L4M TXC-03456
Software Interrupt: A software interrupt indication occurs when one or more interrupt mask bit positions are written with a 1, and the corresponding alarms for those interrupt mask bits occur. The SINT state is exited when the latched alarm causing the interrupt is cleared or the alarm's corresponding interrupt mask bit is written with a 0.
26 27
6
EXTLOS External Transmit Loss Of Signal Alarm: An alarm occurs when a low is present on the EXLOS pin. When control bit EAISEN is a 1, a transmit line AIS is generated. AIPLOC Alarm Indication Port Loss Of Clock: An alarm occurs when the TAIPC clock (which is connected to the mate L4M) has been stuck high or low for 113-764 or more consecutive RAM clock (RAMCI) periods. FEBE and RDI are transmitted as 0 in the G1 byte. Recovery occurs on the first clock transition. New Alarm: When the pointer tracking feature is disabled (PTEN pin is low), this alarm indicates that the J1 pulse has jumped more than three byte positions or has made an illegal increment or decrement. When the pointer tracking feature is enabled (PTEN pin is high), this alarm indicates that 3 x new pointers has been detected. Transmit 140 Mbit/s Loss Of Frame Alarm: An alarm occurs when four consecutive errored frame alignment patterns (based on G.751) are detected. Recovery occurs when three consecutive frame alignment patterns without errors are detected. Receive 140 Mbit/s Loss Of Frame Alarm: An alarm occurs when four consecutive frame alignment patterns (based on G.751) are detected incorrectly. Recovery occurs when three consecutive frame alignment patterns are detected correctly. Transmit Distant Alarm Indication: A 1 indicates that bit 13 in the transmitted 140 Mbit/s G.751 format is a 1. This alarm is inhibited when loss of frame alignment (TLOF), or when a transmit 140 Mbit/s AIS is detected, or when an errored transmit frame is detected (only for that particular errored frame). Receive Distant Alarm Indication: A 1 indicates that bit 13 in the received 140 Mbit/s G.751 format is a 1. This alarm is inhibited on a loss of frame alignment (RLOF), or when a receive 140 Mbit/s AIS is detected, or when an errored receive frame is detected (only for that particular errored frame). Receive Loss Of Pointer Alarm: Enabled when the pointer tracking feature is enabled (PTEN lead is high). An alarm occurs when loss of pointer has been detected in the pointer tracking machine. Receive Path AIS Alarm: Enabled when the pointer tracking feature is enabled (PTEN lead is high). An alarm occurs when path AIS has been detected in the H1 and H2 bytes.
5
2
NEW
28 29
7
TLOF
6
RLOF
5
TDAI
4
RDAI
3
RLOP
2
RPAIS
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
INTERRUPT MASK BIT DEFINITIONS
L4M TXC-03456
The interrupt mask bits work in conjunction with the latched bit positions to provide a hardware and global software interrupt indication. Writing a 1 to one or more mask bits, when the corresponding alarm occurs, will cause the global software interrupt (SINT, Address 26H, bit 7) to occur, and will cause a hardware interrupt to occur by setting the HINT control bit (Address 33H, bit 7) to 1. The hardware interrupt pin will be turned off when the latched alarm bit causing the interrupt is cleared, or when the corresponding interrupt mask bit is set to 0, or the HINT bit is set to 0. The bit positions in the mask bit segment locations correspond to the bit positions in the status register segment locations. Address 30 Bit 7 6 5 4 3 2 1 0 31 7 6 5 4 3 2 1 0 32 7 6 5 4 2 1 0 33 7 6 5 2 Symbol ANOOL TLAISD TFIFOE ABLOJ1 LAISC XAIS DBLOJ1 E1AIS BUSERR RFIFOE RRDI PSLERR C2EQ0 J1LOL J1TIM RLAISD TLOC ABLOC DBLOC RLOC XSTAI XISTAT XPAIS HINT EXTLOS AIPLOC NEW Analyzer Out Of Lock Transmit line 140 Mbit/s AIS Detected Transmit FIFO error (underflowed or overflowed) Add bus loss of J1 Loss of AIS clock External AIS generate signal on EXAIS pin Drop bus loss of J1 AIS detected in the E1 byte (Transport Overhead) Drop bus parity error Receive FIFO error (underflowed or overflowed) Receive RDI/FERF (bit 5 in G1) Path Signal Label error Unequipped C2 status (00H) J1 loss of lock (alignment unstable) J1 Trace identifier mismatch Receive Line AIS Detected Transmit Line Loss Of Clock Add bus loss of clock Drop bus loss of clock Receive line loss of clock External network alarm External STS alarm External Path AIS alarm Hardware interrupt enable External Loss Of Signal alarm Alarm Indication Port Loss of clock alarm 3 consecutive new pointers received Description
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DATA SHEET
Address 34 Bit 7 6 5 4 3 2 Symbol TLOF RLOF TDAI RDAI RLOP RPAIS Description Transmit 140 Mbit/s Loss Of Frame alarm Receive 140 Mbit/s Loss Of Frame alarm Transmit 140 Mbit/s Distant Alarm Indication Receive 140 Mbit/s Distant Alarm Indication Receive Loss Of Pointer Receive Path AIS
L4M TXC-03456
TRANSMIT POH REGISTER DESCRIPTIONS The transmission of the POH byte in the add direction, and the processing of the POH bytes in the drop direction are enabled when a high is placed on the POHDIS lead. Address 68 Bit 7-0 Symbol B3 Error Mask Description B3 Error Mask and Test Byte: When control bit TESTB3 is written with a 0, a 1 written to any of the bit locations will generate a continuous bit error in the corresponding B3 bit position. Internally, this RAM location is exclusiveor gated with the calculated B3 byte prior to transmission. The B3 errors are transmitted until this location is rewritten with a 00H. Bit 7 in this location corresponds to bit 1 in the transmitted B3 byte. When control bit TESTB3 is written with a 1, the bits written into this location are transmitted as the B3 byte.
69
7-0
C2 Signal C2 Signal Label Byte: When control bit EXC2 is a 0, the bits written into this location are transmitted as the C2 byte. When control bits EXC2 and Label POHRAM are a 1, the external POH interface C2 byte is written into this location, and is also transmitted. When control bit EXC2 is a 1, and POHRAM is a 0, the external POH interface C2 byte is transmitted and this location holds the microprocessor-written C2 value. Bit 7 in this location corresponds to bit 1 in the transmitted C2 byte. Transmit G1 Byte Transmit G1 Byte: Bits 7-0 provide the states of the external POH byte or microprocessor-written values, according to the following: 1 7 2 6 3 5 4 4 5 3 6 2 7 1 8 G1 Byte 0 This location
6A
7-0
FEBE
RDI Unassigned
When control bits EXG1, RDIEN, and FEBEEN are 0, the microprocessor writes the transmitted FEBE state and path RDI state. The unassigned bits are always written by the microprocessor unless EXG1 is a 1. When control bits EXG1 and POHRAM are a 1, the external POH interface G1 byte is written into this location, and is also transmitted. When control bit EXG1 is a 1, and POHRAM is a 0, the external POH interface G1 byte is transmitted and this location holds the microprocessor-written G1 value. The unassigned bits for transmission must always be written into bits 2 through 0 in this location, otherwise the transmitted states of these bits are undetermined. See also FEBEEN, RDIEN and RING control bits.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 6B Bit 7-0 Symbol F2 Description
L4M TXC-03456
User Channel: When control bit EXF2 is a 0, the bits written into this location are transmitted as the F2 byte. When control bits EXF2 and POHRAM are a 1, the external POH interface F2 byte is written into this location, and is also transmitted. When control bit EXF2 is a 1, and POHRAM is a 0, the external POH interface F2 byte is transmitted and this location holds the microprocessor-written F2 value. Bit 7 in this location corresponds to bit 1 in the transmitted F2 byte. H4 Byte: When control bit EXH4 is a 0, the bits written into this location are transmitted as the H4 byte. When control bits EXH4 and POHRAM are a 1, the external POH interface H4 byte is written into this location, and is also transmitted. When control bit EXH4 is a 1, and POHRAM is a 0, the external POH interface H4 byte is transmitted and this location holds the microprocessor-written H4 value. Bit 7 in this location corresponds to bit 1 in the transmitted H4 byte. Z3 Byte: When control bit EXZ3 is a 0, the bits written into this location are transmitted as the Z3 byte. When control bits EXZ3 and POHRAM are a 1, the external POH interface Z3 byte is written into this location, and is also transmitted. When control bit EXZ3 is a 1, and POHRAM is a 0, the external POH interface Z3 byte is transmitted and this location holds the microprocessor-written Z3 value. Bit 7 in this location corresponds to bit 1 in the transmitted Z3 byte. Z4 Byte: When control bit EXZ4 is a 0, the bits written into this location are transmitted as the Z4 byte. When control bits EXZ4 and POHRAM are a 1, the external POH interface Z4 byte is written into this location, and is also transmitted. When control bit EXZ4 is a 1, and POHRAM is a 0, the external POH interface Z4 byte is transmitted and this location holds the microprocessor-written Z4 value. Bit 7 in this location corresponds to bit 1 in the transmitted Z4 byte. Z5 Byte: When control bit EXZ5 is a 0, the bits written into this location are transmitted as the Z5 byte. When control bits EXZ5 and POHRAM are a 1, the external POH interface Z5 byte is written into this location, and is also transmitted. When control bit EXZ5 is a 1, and POHRAM is a 0, the external POH interface Z5 byte is transmitted and this location holds the microprocessor-written Z5 value. Bit 7 in this location corresponds to bit 1 in the transmitted Z5 byte. Path Trace Message: The bytes written into this memory segment (16 or 64 bytes determined by the CCITT control bit) will provide a repetitive 64-or 16byte fixed length message for transmission. The 16-byte message is allocated to the 80 to 8FH segment. The remaining segment 90 to BFH is not used. The starting address is not set for transmission. The message is transmitted in a rotating fashion. When control bit EXJ1 is a 0, the bits written into these locations are transmitted as the J1 byte stream. When control bits EXJ1 and POHRAM are a 1, the external POH interface J1 bytes are written into these locations, and are also transmitted. When control bit EXJ1 is a 1, and POHRAM is a 0, the external POH interface J1 bytes are transmitted and this location holds the microprocessor-written J1 values. Bit 7 in this location corresponds to bit 1 in the transmitted J1 byte.
6C
7-0
H4
6D
7-0
Z3
6E
7-0
Z4
6F
7-0
Z5
80 to BF
7-0
J1
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
RECEIVE POH REGISTER DESCRIPTIONS
L4M TXC-03456
The transmission of the POH byte in the add direction, and the processing of the POH bytes in the drop direction is enabled when a high is placed on the POHDIS lead. Address 75 Bit 7-0 Symbol Description
C2 Path Signal Label Compare Byte: The bits in this location are written by C2 Compare the microprocessor and are compared against the received C2 value for path signal label mismatch detection. Bit 7 in this location corresponds to bit 1 in Byte the C2 byte. B3 Byte B3 Received Byte: This location contains the received B3 parity byte value received each frame. Bit errors are counted in a 16-bit counter located at 40H (low order byte) and 41H (high order byte). Block errors (one or more parity errors) are counted in an 8-bit counter located at 4AH. Bit 7 in this location corresponds to bit 1 in the B3 byte. C2 Received Signal Label Byte: This location is the received C2 byte value received each frame. The received C2 byte is compared against the microprocessor-written value in location 75H. Bit 7 in this location corresponds to bit 1 in the C2 byte.
78
7-0
79
7-0
C2 Received Signal Label
7A
7-0
Received Received G1 Byte: This location is the received G1 byte value received each frame. The bit relationship is the following. G1 Byte 1 7 2 6 3 5 4 4 5 3 6 2 7 1 8 G1 Byte 0 This location
FEBE 7B 7C 7D 7E 7F C0 to FF 7-0 7-0 7-0 7-0 7-0 7-0 F2 H4 Z3 Z4 Z5
RDI Unassigned
F2 Received Byte: This location is the received F2 byte value received each frame. Bit 7 in this location corresponds to bit 1 in the F2 byte. H4 Received Byte: This location is the received H4 byte value received each frame. Bit 7 in this location corresponds to bit 1 in the H4 byte. Z3 Received Byte: This location is the received Z3 byte value received each frame. Bit 7 in this location corresponds to bit 1 in the Z3 byte. Z4 Received Byte: This location is the received Z4 byte value received each frame. Bit 7 in this location corresponds to bit 1 in the Z4 byte. Z5 Received Byte: This location is the received Z5 byte value received each frame. Bit 7 in this location corresponds to bit 1 in the Z5 byte.
Received Path Trace Message Microprocessor Read feature: The received J1 message bytes are stored into this memory segment. The 16-byte message is J1 Message allocated to the C0H to CFH memory segment, when control bit CCITT is a 1. When CCITT is 0, the memory segment is configured for 64 bytes. The incoming message is written in with no specific starting address, and in a rotating fashion, and any incoming J1 byte is written into the next sequential RAM location. However, when CCITT and J1COM are both set to 1 and the received 16-byte J1 message has a valid multiframe alignment pattern and is stable (J1LOL=0), the bits written into C0H-CFH will be aligned such that the J1 Byte with the start of multiframe indication will be in location C0H. The values in C0H to CFH will be the "debounced" stable message.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address F0 to FF Bit 7-0 Symbol Description
L4M TXC-03456
Compare Path Trace Message Compare feature: The microprocessor writes into this 16-byte memory segment the expected J1 message (multiframe bits and J1 Message CRC as required) when CCITT is 1 and J1COM is 1. This message is then compared against the received J1 byte for the correct message. The starting address of the message must be written to location F0H (multiframe value of 1). The L4M performs the alignment of the incoming message against this message segment.
PERFORMANCE COUNTERS DESCRIPTIONS All performance counters globally can be configured to be either saturating or non-saturating with a roll over in count. Writing a 1 to control bit COR (bit 0 in register location 13H) conditions all counters to be non-saturating. Reading a non-saturating counter will not clear the counter. When the counters are configured to be saturating, the counter will clear on a microprocessor read cycle. All performance counters are cleared simultaneously when a 1 is written to control bit RSETC. This bit is self clearing and does not require a 0 to be written to it. When reading a 16-bit counter, the low order byte must be read first. Address 40 41 Bit 7-0 Symbol B3 Counter Description B3 Byte Parity Error 16-bit counter: Counts the number of B3 BIP-8 parity error indications that have been detected between the received B3 value and the calculated value. The low order counter value is held in location 40H. The high order counter value is in held in location 41H. Bit 0 in 40H is the LSB. Far End Block Error 16-bit Counter: When control bit FEBEBC is a 0, this counter counts the number of FEBE error count indications received in bits 1 through 4 of the G1 byte. The maximum number of errors counted per frame is 8. Values other than between 1 thru 8 are counted as 0 errors. The low order counter value is held in location 42H. The high order counter value is in held in location 43H. When control bit FEBEBC is a 1, the number of FEBE blocks in error are counted instead of the FEBE count. Bit 0 in 42H is the LSB. Analyzer 16-bit Error Counter: Enabled when control bit ANAEN is a 1, and when the analyzer is in lock. Counts the number of errors received in the received 223-1 PRBS pattern. The low order counter value is held in location 44H. The high order counter value is in held in location 45H. Bit 0 in 44H is the LSB. Transmit 140 Mbit/s Framing Pattern 16-bit Error Counter: After frame alignment, this counter counts the number of transmit errored framing patterns in the G.751 signal. The low order counter value is held in location 46H. The high order counter value is in held in location 47H. Bit 0 in 46H is the LSB. Receive 140 Mbit/s Framing Pattern 16-bit Error Counter: Enabled when control bit BSAISE is a 0 or when BSAISE is 1 and the L4M is not generating a receive AIS. After frame alignment, this counter counts the number of received errored framing patterns in the G.751 signal. The low order counter value is held in location 48H. The high order counter value is in held in location 47H. Bit 0 in 48H is the LSB.
42 43
7-0
FEBE Counter
44 45
7-0
Analyzer Counter
46 47
7-0
Transmit Framing Error Counter Receive Framing Error Counter
48 49
7-0
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
Address 4A 4B Bit 7-0 7-0 Symbol B3 Block Counter Description
L4M TXC-03456
B3 8-bit Block Error Counter: Counts the number of B3 blocks that are received in error. Bit 0 is the LSB.
Positive Justification 8-bit Counter: Counts the number of positive justiPositive Justification fications based on the incoming J1 pulse. When the pointer tracking feature is enabled, counts the number of pointer increments. Bit 0 is the LSB. Counter Negative Negative Justification 8-bit Counter: Counts the number of negative Justification justifications based on the incoming J1 pulse. When the pointer tracking feature is enabled, counts the number of pointer decrements. Bit 0 is the Counter LSB. NDF Counter New Data Flag 8-bit Counter. Enabled when a high is placed on PTEN (pin2), the pointer tracking feature. Counts the number of received NDF (1001, 0001, 1101, 1011, and 1000) detected in bits 1-4 of H11. This counter does not count the NDF in the AIS to NDF state transition of the pointer tracking state machine. Desynchronizer Pointer Offset Counter: A 9-bit counter, plus a sign bit, that provides the count of the internal pointer offset counter (i.e., pointer leak buffer offset counter, which is the number of bits that have to be leaked out if the sign bit is 0, or the number of leak times not to leak out a bit if the sign bit is 1) for a microprocessor read cycle, when required. The MSB bit is located in bit 0 in 4FH, followed by bit 7 in 4EH. The sign bit is located in bit 1 in 4FH. The value provided is in the 2's complement form, with a zero value equal to 0. This counter can be used in setting the FLR registers. Further information on this subject is provided in a TranSwitch Application Note, document number TXC-03456-0001-AN, Ed. 1, February 7, 1995.
4C
7-0
4D
7-0
4E 4F
7-0 1-0
Desyn Pointer Offset Counter
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET PACKAGE INFORMATION
L4M TXC-03456
The L4M device is packaged in a 144-pin plastic quad flat package (PQFP) suitable for socket or surface mounting, as illustrated in Figure 28.
108 109 73 72 See Details "B" and "C"
TRANSWITCH
TXC-03456AIPQ
0.65(TYP) Detail "B" 0.22(MIN) 0.38(MAX) 144 37 1 INDEX PIN #1 22.75 (SQ) 28.00 (SQ) 31.20 (SQ) 36 Detail "C"
(TYP)
4.07 (MAX) SEE DETAIL "A" 0.16 TYP. 0.25 (MIN)
3.42
0 -7 DEGREES TYP .
DETAIL "A"
0.80 TYP .
Notes: 1. All linear dimensions are in millimeters. 2. All dimensions are nominal unless otherwise indicated. 3. Falls within JEDEC MO-108.
Figure 28. L4M TXC-03456 144-Pin Plastic Quad Flat Package
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET ORDERING INFORMATION
Part Number: TXC-03456AIPQ 144-Pin Plastic Quad Flat Package
L4M TXC-03456
RELATED PRODUCTS
TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock and Data Output). This device is similar to the SYN155. It has both clock and data outputs on the line side. TXC-03003B, SOT-3 VLSI Device (STM-1/STS-3/STS-3c Overhead Terminator). This is a dual-mode device, which can be configured either to emulate the TXC-03003 device or to provide additional capabilities.
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET STANDARDS DOCUMENTATION SOURCES
L4M TXC-03456
Telecommunication technical standards and reference documentation may be obtained from the following organizations:
ANSI (U.S.A.): American National Standards Institute 11 West 42nd Street New York, New York 10036 The ATM Forum (U.S.A., Europe, Asia): 2570 West El Camino Real Suite 304 Mountain View, CA 94040 ATM Forum Europe Office Av. De Tervueren 402 1150 Brussels Belgium ATM Forum Asia-Pacific Office Hamamatsucho Suzuki Building 3F 1-2-11, Hamamatsucho, Minato-ku Tokyo 105-0013, Japan Bellcore (See Telcordia) CCITT (See ITU-T) EIA (U.S.A.): Electronic Industries Association Global Engineering Documents 7730 Carondelet Avenue, Suite 407 Clayton, MO 63105-3329 ETSI (Europe): European Telecommunications Standards Institute 650 route des Lucioles 06921 Sophia Antipolis Cedex France Tel: 4 92 94 42 22 Fax: 4 92 94 43 33 Web: www.etsi.org Tel: 800-854-7179 (within U.S.A.) Tel: 314-726-0444 (outside U.S.A.) Fax: 314-726-6418 Web: www.global.ihs.com Tel: 3 3438 3694 Fax: 3 3438 3698 Web: www.apinfo@atmforum.com Tel: 2 761 66 77 Fax: 2 761 66 79 Web: www.euroinfo@atmforum.ocm Tel: 650-949-6700 Fax: 650-949-6705 Web: www.atmforum.org Tel: 212-642-4900 Fax: 212-302-1286 Web: www.ansi.org
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET
L4M TXC-03456
GO-MVIP (U.S.A.): The Global Organization for Multi-Vendor Integration Protocol (GO-MVIP) 3220 N Street NW, Suite 360 Washington, DC 20007 ITU-T (International): Publication Services of International Telecommunication Tel: 22 730 5111 Union Telecommunication Standardization Sector Fax: 22 733 7256 Place des Nations, CH 1211 Web: www.itu.int Geneve 20, Switzerland MIL-STD (U.S.A.): DODSSP Standardization Documents Ordering Desk Building 4 / Section D 700 Robbins Avenue Philadelphia, PA 19111-5094 PCI SIG (U.S.A.): PCI Special Interest Group 2575 NE Kathryn Street #17 Hillsboro, OR 97124 Tel: 800-433-5177 (within U.S.A.) Tel: 503-693-6232 (outside U.S.A.) Fax: 503-693-8344 Web: www.pcisig.com Tel: 215-697-2179 Fax: 215-697-1462 Web: www.dodssp.daps.mil Tel: 800-669-6857 (within U.S.A.) Tel: 903-769-3717 (outside U.S.A.) Fax: 508-650-1375 Web: www.mvip.org
Telcordia (U.S.A.): Telcordia Technologies, Inc. Attention - Customer Service 8 Corporate Place Piscataway, NJ 08854 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsucho - Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or.jp Tel: 800-521-CORE (within U.S.A.) Tel: 908-699-5800 (outside U.S.A.) Fax: 908-336-2559 Web: www.telcordia.com
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TXC-03456-MB Ed. 1A, January 2000
DATA SHEET LIST OF DATA SHEET CHANGES
L4M TXC-03456
This change list identifies those areas within this updated L4M Data Sheet that have significant differences relative to the previous, and now superseded, L4M Data Sheet: Updated L4M Data Sheet: Previous L4M Data Sheet: Edition 1A, January 2000. PRELIMINARY Edition 1, June 1995.
The page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. Page Number of Updated Data Sheet All All 2 19 89 90 91 93 95
Summary of the Change Changed edition number and date. Removed PRELIMINARY document status markings (and associated explanatory text on pages 1 and 93). Updated Table of Contents. Deleted third and fifth row of first table. Changed Max value and deleted Typ value in second table. Added part number to diagram for Figure 28. Changed content of "Related Products" section. Changed content of "Standards Documentation Sources" section. Added "List of Data Sheet Changes" section. Changed content of "Documentation Update Registration Form" section.
TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. TranSwitch assumes no liability for TranSwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TranSwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TranSwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
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TXC-03456-MB Ed. 1A, January 2000
TranSwitch Corporation
*
3 Enterprise Drive
*
Shelton, CT 06484 USA
*
Tel: 203-929-8810
*
Fax: 203-926-9453
*
www.transwitch.com
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DATA SHEET DOCUMENTATION UPDATE REGISTRATION FORM
L4M TXC-03456
If you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the Marketing Communications Department at TranSwitch. Marketing Communications will ensure that the relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453), or by e-mail (info@txc.com), or by telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www.transwitch.com). Name: ________________________________________________________________________________ Company: ___________________________________________ Title: ______________________________ Dept./Mailstop: __________________________________________________________________________ Street: ________________________________________________________________________________ City/State/Zip: __________________________________________________________________________ If located outside U.S.A., please add - Country: _______________ Telephone: ________________________ Postal Code: ___________________
Ext.: _____________ Fax: __________________________
E-mail: ________________________________________________ Please provide the following details for the managers in charge of the following departments at your company location. Department Company/Division Engineering Marketing Title __________________ __________________ __________________ Name __________________ __________________ __________________
Please describe briefly your intended application(s) and indicate whether you would like to have a TranSwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ If you are also interested in receiving updated documentation for other TranSwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________
Please fold, tape and mail this page (see other side) or fax it to Marketing Communications at 203.926.9453.
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TXC-03456-MB Ed. 1A, January 2000
(Fold back on this line second, then tape closed, stamp and mail.)
3 Enterprise Drive Shelton, CT 06484-4694 U.S.A.
First Class Postage Required
TranSwitch Corporation
Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A.
(Fold back on this line first.)
Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available.
TranSwitch Corporation
*
3 Enterprise Drive
*
Shelton, CT 06484 USA
*
Tel: 203-929-8810
*
Fax: 203-926-9453
*
www.transwitch.com

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